RSTN

RESET/EN

VCC

VSADJ_CFG0

VCC

GND

DA0P

DA0N

DB0P

DB0N

HS RX

LP RX/TX

HS TX

LP RX/TX

CHANNEL

CONTROL

DA1P

DA1N

DB1P

DB1N

HS RX

LP RX

HS TX

LP TX

CHANNEL

CONTROL

DACP

DACN

DBCP

DBCN

HS RX

LP RX

HS TX

LP TX

CHANNEL

CONTROL

DA2P

DA2N

DB2P

DB2N

HS RX

LP RX

HS TX

LP TX

CHANNEL

CONTROL

DA3P

DA3N

DB3P

DB3N

HS RX

LP RX

HS TX

LP TX

CHANNEL

CONTROL

ERC/SDA

EQ/SCL

CSR

Space

PRE_CFG1

VREG_OUT

VREG

LDO

I2C

Slave

Copyright © 2016, Texas Instruments Incorporated

10

SN65DPHY440SS, SN75DPHY440SS

SLLSEO9A – MARCH 2016 – REVISED APRIL 2016

www.ti.com

Product Folder Links: SN65DPHY440SS SN75DPHY440SS

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Copyright © 2016, Texas Instruments Incorporated

7 Detailed Description

7.1 Overview

The DPHY440SS is a one to four lane and clock MIPI DPHY re-driver that regenerates the DPHY signaling. The

device complies with MIPI DPHY 1.1 standard and can be used in either a MIPI CSI-2 or MIPI DSI application at

datarates of up to 1 Gbps

The device compensates for PCB, connector, and cable related frequency loss and switching related loss to

provide the optimum electrical performance from a CSI2/DSI source to sink. The DPHY440 DPHY inputs feature

configurable equalizers.

The output pins will automatically compensate for uneven skew between clock and data lanes. The DPHY440

output swing and edge rate can be adjusted by changing the state of the VSADJ_CFG0 pin and ERC pin

respectively.

The DPHY440 is optimized for mobile applications, and contains activity detection circuitry on the DPHY Link

interface that can transition into a lower power mode when in ULPS and LP states.

The device is characterized for an extended operational temperature range from –40ºC to 85ºC.

7.2 Functional Block Diagram