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SN75DPHY440SSRHRR Datasheet(PDF) 8 Page - Texas Instruments |
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SN75DPHY440SSRHRR Datasheet(HTML) 8 Page - Texas Instruments |
8 / 31 page SCL SDA tHD;STA tLOW tr tHD;DAT tHIGH tf tSU;DAT tSU;STA tSU;STO tf START REPEATED START STOP tHD;STA START tSP tr BUF t 8 SN65DPHY440SS, SN75DPHY440SS SLLSEO9A – MARCH 2016 – REVISED APRIL 2016 www.ti.com Product Folder Links: SN65DPHY440SS SN75DPHY440SS Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated (1) (1) All typical values are at VCC = 3.3 V, and TA = 25°C. 6.8 Switching Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT I2C (ERC (SDA), EQ (SCL)) F(SCL) I2C Clock Freqency 100 kHz tF_I2C Fall time of both SDA and SCL signals Load of 350 pF with 2-K pullup resistor. Measure at 30% - 70% 300 ns tR_I2C Rise Time of both SDA and SCL signals 1000 ns DPHY LINK F(BR) Bit Rate 1 Gbps F(HSCLK) HS Clock Input range 100 500 µsMHz F(DESKEW) Automatic Deskew range 220 500 MHz MIPI DPHY HS Receiver Interface (DA0P/N, DA1P/N, DA2P/N, DA3P/N, DACP/N) ∆V(CMRX_HF) Common-mode Interface beyond 450 MHz 100 mV ∆V(CMRX_LF) Common-mode interference 50 MHz – 450 MHz –50 50 mV MIPI DPHY HS Transmitter Interface (DB0P/N, DB1P/N, DB2P/N, DB3P/N, DBCP/N) ∆V(CMRX_HF) Common-level variations above 450 MHz 5 mVrms ∆V(CMRX_LF) Common-level variation between 50 MHz – 450 MHz. 25 mVpeak tR and tF 20% - 80% rise time and fall time Datarate ≤ 1 Gbps 0.3 ns 100 ns MIPI DPHY LP Receiver Interface (DA0P/N, DA1P/N, DA2P/N, DA3P/N, DACP/N, DB0P/N) eSPIKE Input Pulse rejection 300 V ps tMIN(RX) Minimum pulse width response 20 ns V(INT) Peak interference amplitude 200 mv F(INT) Interference Frequency 450 Mhz t(LP-PULSE-RX) Pulse Width of the XOR of DAxP and DAxN First LP XOR clock pulse after Stop state or last pulse before Stop state. 42 ns All other pulses. 22 ns MIPI DPHY LP Transmitter Interface (DB0P/N, DB1P/N, DB2P/N, DB3P/N, DBCP/N, DA0P/N) tREOT 30% - 85% rise time and fall time Measured at end of HS transmission. 35 ns t(LP-PULSE-TX) Pulse Width of the LP XOR clock First LP XOR clock pulse after Stop state or last pulse before Stop state 40 ns All other pulses 20 ns t(LP-PER-TX) Period of the LP XOR clock 90 ns δV/δtsr Slew Rate at CLOAD = 70 pF 150 mV/ns Slew Rate at CLOAD = 0 pF Fallng edge only 30 mV/ns Slew Rate at CLOAD = 0 pF Rising edge only 30 mV/ns CLOAD Load Capacitance 70 pF Figure 1. I2C Timing |
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