1

FEATURES

9

10

16

15

14

13

12

11

1

2

3

4

5

6

7

8

GND

RO2

RO1

DI1

DI2

ED

ER

RI1

RI1

RI2

RI2

DO1

DO1

DO2

DO2

DW AND D PACKAGE

(TOP VIEW)

DESCRIPTION

DI1

DI2

ED

ER

RO2

RO1

RI1

RI1

RI2

RI2

DO1

DO1

DO2

DO2

Enable Truth Table

TB5T1

SLLS589C – NOVEMBER 2003 – REVISED OCTOBER 2007

www.ti.com

DUAL DIFFERENTIAL PECL DRIVER/RECEIVER

In circuits with termination resistors, the line remains

impedance- matched when the circuit is powered

• Functional Replacement for the Agere BTF1A

down. The driver does not load the line when it is

• Driver Features

powered down.

–

Third-State Logic Low Output

All devices are characterized for operation from -40

°C

–

ESD Protection HBM > 3 kV, CDM > 2 kV

to 85

°C.

–

The logic inputs of this device include internal pull-up

–

Capable of Driving 50-

Ω loads

resistors of approximately 40 k

Ω that are connected

–

2.0-ns Maximum Propagation Delay

are open circuited.

–

0.2-ns Output Skew (typical)

PIN ASSIGNMENTS

• Receiver Features

–

High-Input Impedance Approximately 8 k

Ω

–

4.0-ns Maximum Propagation Delay

–

50-mV Hysteresis

–

Slew Rate Limited (1 ns min 80% to 20%)

–

ESD Protection HBM > 3 kV, CDM > 2 kV

–

-1.1-V to 7.1-V Input Voltage Range

• Common Device Features

–

Common Enable for Each Driver/Receiver

Pair

FUNCTIONAL BLOCK DIAGRAM

–

Operating Temperature Range: -40

°C to

85

°C

–

Single 5.0 V ± 10% Supply

–

Available in Gull-Wing SOIC (JEDEC

MS-013, DW) and SOIC (D) Package

The TB5T1 device is a dual differential driver/receiver

circuit that transmits and receives digital data over

balanced

transmission

lines.

The

dual

drivers

translate

input

TTL

logic

levels

to

differential

pseudo-ECL output levels. The dual receivers convert

differential-input logic levels to TTL output levels.

Each driver or receiver pair has its own common

enable control allowing serial data and a control clock

to be transmitted and received on a single integrated

circuit. The TB5T1 requires the customer to supply

ED

ER

D1

D2

R1

R2

termination resistors on the circuit board.

0

0

Active

Active

Active

Active

The

power-down

loading

characteristics

of

the

1

0

Disabled

Disabled

Active

Active

receiver input circuit are approximately 8 k

Ω relative

0

1

Active

Active

Disabled

Disabled

to the power supplies; hence, it does not load the

1

1

Disabled

Disabled

Disabled

Disabled

transmission line when the circuit is powered down.

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Copyright © 2003–2007, Texas Instruments Incorporated

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.