SDA

SCL

Data Line

Stable;

Data Valid

Change

of Data

Allowed

TCA9546A

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SCPS205A – APRIL 2014 – REVISED FEBRUARY 2015

9.3 Feature Description

allow 1.8-V, 2.5-V, or 3.3-V parts to communicate with 5-V parts. Additionally, in the event that communication on

feature or by a power-on reset which results from cycling power to the device.

9.4 Device Functional Modes

9.4.1

RESET Input

The RESET input is an active-low signal that may be used to recover from a bus-fault condition. When this signal

9.4.2 Power-On Reset

9.5 Programming

data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pullup

resistor when connected to the output stages of a device. Data transfer can be initiated only when the bus is not

busy.

One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the high

period of the clock pulse, as changes in the data line at this time are interpreted as control signals (see Figure 7).

Figure 7. Bit Transfer

Both data and clock lines remain high when the bus is not busy. A high-to-low transition of the data line while the

clock is high is defined as the start condition (S). A low-to-high transition of the data line while the clock is high is

defined as the stop condition (P) (see Figure 8).

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