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TCI6636K2H Datasheet(PDF) 3 Page - Texas Instruments |
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TCI6636K2H Datasheet(HTML) 3 Page - Texas Instruments |
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3 / 362 page  Multicore DSP+ARM KeyStone II System-on-Chip (SoC) Copyright 2013 Texas Instruments Incorporated TCI6636K2H Features and Description 3 SPRS835F—October 2013 TCI6636K2H Submit Documentation Feedback The TCI6636K2H contains many wireless basestation coprocessors to offload the bulk of the processing demands of layer 1 and layer 2 basestation processing. This keeps the cores free for receiver algorithms and other differentiating functions. The SoC contains multiple copies of key coprocessors such as the FFTC and TCP3d. A key coprocessor for enabling high data rates is the Bit Rate Coprocessor (BCP), which handles the entire downlink bit-processing chain and much of the receive bit processing. The architectural elements of the SoC (Multicore Navigator) ensure that all the bits are processed without any CPU intervention or overhead, allowing the system to make optimal use of its resources. TI's scalable multicore SoC architecture solutions provide developers with a range of software-compatible and hardware-compatible devices to minimize development time and maximize reuse across all basestation platforms from Femto to Macro. The TCI6636K2H device has a complete set of development tools that includes: a C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows debugger interface for visibility into source code execution. 1.5 Enhancements in KeyStone II The KeyStone II architecture provides many major enhancements over the previous KeyStone I generation of devices. The KeyStone II architecture integrates an ARM Cortex-A15 processor quad-core cluster to enable Layer 2 (MAC/RLC) and higher layer processing. The number of DSP cores and FFTC accelerators has been doubled for 2× improvement in Layer 1 processing. The external memory bandwidth has been doubled with the integration of dual DDR3 1600 EMIFs. MSMC internal memory bandwidth is quadrupled with MSMC V2 architecture improvements. Multicore Navigator supports 2× the number of queues, descriptors and packet DMA, 4× the number of micro RISC engines and a significant increase in the number of push/pops per second, compared to the previous generation. The new peripherals that have been added include the USB 3.0 controller, USIM interface controller, and Asynchronous EMIF controller for NAND/NOR memory access. The 2-port Gigabit Ethernet switch in KeyStone I has been replaced with a 4-port Gigabit Ethernet switch in KeyStone II. Time synchronization support has been enhanced to reduce software workload and support additional standards like IEEE1588 Annex D/E and SyncE. The number of GPIOs and serial interface peripherals like I 2C and SPI have been increased to enable more board level control functionality. |
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