TCM8002

DATA PROCESSOR FOR CELLULAR TELEPHONE

SLWS008C − SEPTEMBER 1994 − REVISED JUNE 1996

7

POST OFFICE BOX 655303

POST OFFICE BOX 1443

noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VOH

High-level output voltage

IOH = − 2 mA

VDD −0.8

V

VOL

Low-level output voltage

IOL = 2 mA

0.5

V

VIT +

Positive-going input threshold voltage

0.7 VDD

V

VIT −

Negative-going input threshold voltage

0.2 VDD

V

Vhys

Hysteresis (VIT + − VIT −)

0.1 VDD

0.3 VDD

V

IOZ

High-impedance output current

VI = VDD or VSS

±10

µA

IIL

Low-level input current

VI = VSS

−1

µA

IIH

High-level input current

VI = VDD

1

µA

IO

Pullup output current

VI = VSS

− 7.2

− 14.84

− 24.47

µA

Default mode

3.6

IDD

Supply current with 2.56-MHz crystal

Low-power mode

2.8

mA

IDD

Supply current with 2.56-MHz crystal

Low-power mode, SAT off

2.5

mA

timing requirements over recommended ranges of operating conditions (see Figure 1)

MIN

MAX

UNIT

tsu1

Setup time, CS low before DCLK

↑

300

ns

th1

Hold time, CS low after DCLK

↓

300

ns

tsu2

Setup time, DATAIN before DCLK

↑

300

ns

th2

Hold time, DATAIN after DCLK

↑

300

ns

tc

DCLK clock period (nominal)

1

µs

tc(er)

DCLK clock period, Read start bit − Event Register

2

µs

tc(or)

DCLK clock period, Read start bit − Other Register

1

µs

Period that CS must be high between read or write operations

100

ns