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23A640 Datasheet(PDF) 6 Page - Microchip Technology |
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23A640 Datasheet(HTML) 6 Page - Microchip Technology |
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6 / 28 page  23A640/23K640 DS22126E-page 6 2008-2011 Microchip Technology Inc. 2.0 FUNCTIONAL DESCRIPTION 2.1 Principles of Operation The 23X640 is a 8192-byte Serial SRAM designed to interface directly with the Serial Peripheral Interface (SPI) port of many of today’s popular microcontroller families, including Microchip’s PIC® microcontrollers. It may also interface with microcontrollers that do not have a built-in SPI port by using discrete I/O lines programmed properly in firmware to match the SPI protocol. The 23X640 contains an 8-bit instruction register. The device is accessed via the SI pin, with data being clocked in on the rising edge of SCK. The CS pin must be low and the HOLD pin must be high for the entire operation. Table 2-1 contains a list of the possible instruction bytes and format for device operation. All instructions, addresses and data are transferred MSB first, LSB last. Data (SI) is sampled on the first rising edge of SCK after CS goes low. If the clock line is shared with other peripheral devices on the SPI bus, the user can assert the HOLD input and place the 23X640 in ‘HOLD’ mode. After releasing the HOLD pin, operation will resume from the point when the HOLD was asserted. 2.2 Modes of Operation The 23A256/23K256 has three modes of operation that are selected by setting bits 7 and 6 in the STATUS register. The modes of operation are Byte, Page and Burst. Byte Operation – is selected when bits 7 and 6 in the STATUS register are set to 00. In this mode, the read/ write operations are limited to only one byte. The Command followed by the 16-bit address is clocked into the device and the data to/from the device is transferred on the next 8 clocks (Figure 2-1, Figure 2-2). Page Operation – is selected when bits 7 and 6 in the STATUS register are set to 10. The 23A640/23K640 has 1024 pages of 32 Bytes. In this mode, the read and write operations are limited to within the addressed page (the address is automatically incremented internally). If the data being read or written reaches the page boundary, then the internal address counter will increment to the start of the page (Figure 2-3, Figure 2-4). Sequential Operation – is selected when bits 7 and 6 in the STATUS register are set to 01. Sequential opera- tion allows the entire array to be written to and read from. The internal address counter is automatically incremented and page boundaries are ignored. When the internal address counter reaches the end of the array, the address counter will roll over to 0x0000 (Figure 2-5, Figure 2-6). 2.3 Read Sequence The device is selected by pulling CS low. The 8-bit READ instruction is transmitted to the 23X640 followed by the 16-bit address, with the first MSB of the address being a “don’t care” bit. After the correct READ instruction and address are sent, the data stored in the memory at the selected address is shifted out on the SO pin. If operating in Page mode, after the first byte of data is shifted out, the next memory location on the page can be read out by continuing to provide clock pulses. This allows for 32 consecutive address reads. After the 32nd address read the internal address counter wraps back to the byte 0 address in that page. If operating in Sequential mode, the data stored in the memory at the next address can be read sequentially by continuing to provide clock pulses. The internal Address Pointer is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached (1FFFh), the address counter rolls over to address 0000h, allowing the read cycle to be continued indefinitely. The read operation is terminated by raising the CS pin (Figure 2-1). 2.4 Write Sequence Prior to any attempt to write data to the 23X640, the device must be selected by bringing CS low. Once the device is selected, the Write command can be started by issuing a WRITE instruction, followed by the 16-bit address, with the first three MSBs of the address being a “don’t care” bit, and then the data to be written. A write is terminated by the CS being brought high. If operating in Page mode, after the initial data byte is shifted in, additional bytes can be shifted into the device. The Address Pointer is automatically incremented. This operation can continue for the entire page (32 Bytes) before data will start to be overwritten. If operating in Sequential mode, after the initial data byte is shifted in, additional bytes can be clocked into the device. The internal Address Pointer is automati- cally incremented. When the Address Pointer reaches the highest address (1FFFh), the address counter rolls over to (0000h). This allows the operation to continue indefinitely, however, previous data will be overwritten. |
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