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THS1215 Datasheet(PDF) 5 Page - Texas Instruments |
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THS1215 Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 22 page  www.ti.com ELECTRICAL CHARACTERISTICS THS1215 SLAS292A – MARCH 2001 – REVISED MARCH 2004 over recommended operating conditions (AV DD = DVDD = 3.3 V, fs = 15 MHz/50% duty cycle, MODE = 1, 1-V input span, internal reference, T min to Tmax) (unless otherwise noted) DIGITAL INPUTS AND OUTPUTS (all supplies = 3.3 V) PARAMETER TEST CONDITION MIN TYP MAX UNIT DIGITAL INPUTS All other inputs 0.8 × DV DD VIH High level input voltage CLK 0.8 × AV DD V All other inputs 0.2 × DV DD VIL Low level input voltage CLK 0.2 × AV DD IIH High level input current 1 µA IIL Low level input current –1 Ci Input capacitance 5 pF DIGITAL OUTPUTS VOH High level output voltage Iload = 50 µA DVDD–0.4 V VOL Low level output voltage Iload = –50 µA 0.4 V High impedance output current ±1 µA tr/tf Rise/fall time CL = 10 pF 4.5 ns ANALOG INPUTS Ci Switched input capacitance 6 pF td(ap) Aperture delay time 2 ns Aperture uncertainty (jitter) 2 ns DC leakage current (input = ±FS) 10 µA POWER SUPPLY (CLK = 15 MHz) XVDD Supply voltage (all supplies) 3 3.3 3.6 V IDD Supply current active - total 45 53.5 mA I(analog) Supply current active - analog 34 mA I(digital) Supply current active - digital 11 mA II(standby) Standby supply current CLK = 0 MHz 10 µA 1 µF bypass (1) 770 µs t(PU) Power-up time for references from standby 10 µF bypass (1) 6.2 ms t(PUconv) Power-up time for valid ADC conversion 1 µF bypass (2) 820 ns Clock = 15 MHz, AIN+ and AIN– at Common 148 177 Mode or 1.65 V dc PD Power dissipation mW Clock = 15 MHz, 167 fin = 3.58 MHz at –1 dBFS PD(STBY) Standby power dissipation CLK = 0 MHz 36 µW PSRR Power supply rejection ratio ±0.1 %FS (1) Time for reference to recover to 1% of its final voltage level. (2) Time for ADC conversions to be accurate to within 0.1% of fullscale. 5 Not Recommended For New Designs |
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