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TL16C2752IFNR Datasheet(PDF) 5 Page - Texas Instruments |
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TL16C2752IFNR Datasheet(HTML) 5 Page - Texas Instruments |
5 / 26 page Detailed Description Hardware Autoflow Control (see Figure 1) RCV FIFO Serial to Parallel Flow Control XMT FIFO Parallel to Serial Flow Control Parallel to Serial Flow Control Serial to Parallel Flow Control XMT FIFO RCV FIFO ACE1 ACE2 D7 −D0 RX TX RTS CTS TX RX CTS RTS D7 −D0 TL16C2752 www.ti.com ................................................................................................................................................ SLWS188A – JUNE 2006 – REVISED SEPTEMBER 2008 TERMINAL FUNCTIONS (continued) TERMINAL I/O DESCRIPTION NAME FN NO. RHB NO. Reset. RESET will reset the internal registers and all the outputs. The UART transmitter RESET 21 12 I output and the receiver input are disabled during reset time. See TL16C2752 external reset conditions for initialization details. RESET is an active-high input. Ring indicator (active low). These inputs are associated with individual UART channels A and B. A logic low on these pins indicates the modem has received a ringing signal from the RIA, 43, – I telephone line. A low-to-high transition on these input pins generates a modem status RIB 31 interrupt, if enabled. The state of these inputs is reflected in the modem status register (MSR). These inputs should be pulled high if unused. Request to send (active low). These outputs are associated with individual UART channels A and B. A low on the RTS pin indicates the transmitter has data ready and waiting to send. RTSA, 36, 22, Writing a 1 in the modem control register (MCR bit 1) sets these pins to low, indicating data is O RTSB 23 13 available. After a reset, these pins are set to high. These pins only affects the transmit and receive operation when auto RTS function is enabled through the enhanced feature register (EFR) bit 6, for hardware flow control operation. Receive data input. These inputs are associated with individual serial channel data to the RXA, 39, 24, I TL16C2752. During the local loopback mode, these RX input pins are disabled and TX data is RXB 25 15 internally connected to the UART RX input internally. Transmit data. These outputs are associated with individual serial transmit channel data from TXA, 38, 23, O the TL16C2752. During the local loopback mode, the TX input pin is disabled and TX data is TXB 26 16 internally connected to the UART RX input. TXRDYA, 1, Transmit ready (active low). TXRDY A and B go low when there are at least a trigger-level – O TXRDYB 32 number of spaces available. They go high when the TX buffer is full. VCC 33, 44 26 I Power-supply inputs Crystal or external clock. XTAL1 functions as a crystal input or as an external clock input. A crystal can be connected between XTAL1 and XTAL2 to form an internal oscillator circuit (see XTAL1 11 4 I Figure 4). Alternatively, an external clock can be connected to XTAL1 to provide custom data rates. Crystal oscillator or buffered clock (see also XTAL1). XTAL2 is used as a crystal oscillator XTAL2 13 5 O output or buffered a clock output. Hardware autoflow control is comprised of auto-CTS and auto-RTS. With auto-CTS, the CTS input must be active before the transmitter FIFO can emit data. With auto-RTS, RTS becomes active when the receiver needs more data and notifies the sending serial device. When RTS is connected to CTS, data transmission does not occur unless the receiver FIFO has space for the data; thus, overrun errors are eliminated using ACE1 and ACE2 from a TLC16C2752 with the autoflow control enabled. If not, overrun errors can occur when the transmit data rate exceeds the receiver FIFO read latency. Figure 1. Autoflow Control (Auto-RTS and Auto-CTS) Example Copyright © 2006–2008, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Link(s): TL16C2752 |
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