 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
DS21448 Datasheet(PDF) 9 Page - Dallas Semiconductor |
|
||||||||||||||||||||||||||||||
DS21448 Datasheet(HTML) 9 Page - Dallas Semiconductor |
|
|
9 / 60 page  DS21448 3.3V T1/E1/J1 Quad Line Interface 9 of 60 Table 2-C. Parallel Interface Mode Pin Description PIN I/O FUNCTION RD (DS) I Read Input (Data Strobe). RD and DS are active-low signals. DS is active low when in nonmultiplexed, Motorola mode. See the bus timing diagrams in Section 10. WR (R/W) I Write Input (Read/Write). WR is an active-low signal. See the bus timing diagrams in Section 10. ALE (AS) I Address Latch Enable (Address Strobe). When using multiplexed bus mode (BIS0 = 0), this pin serves to demultiplex the bus on a positive-going edge. In nonmultiplexed bus mode (BIS0 = 1), ALE should be wired low. A4–A0 I Address Bus. In nonmultiplexed bus operation (BIS0 = 1), these pins serve as the address bus. In multiplexed bus operation (BIS0 = 0), these pins are not used and should be wired low. D7/AD7–D0/AD0 I/O Data Bus/Address/Data Bus. In nonmultiplexed bus operation (BIS0 = 1), these pins serve as the data bus. In multiplexed bus operation (BIS0 = 0), these pins serve as an 8-bit multiplexed address/data bus. INT O Interrupt ( INT). The interrupt flags the host controller during conditions and change of conditions defined in the status register. It is an active-low, open-drain output. TXDIS/TEST I Tri-State Control, Multifunctional. Set this pin high, with all CS1–CS4 inputs inactive, to tri-state TTIP1–TTIP4 and TRING1–TRING4. Set this pin high with any of the CS1–CS4 inputs active to tri-state all outputs and I/O pins (including the parallel control port). Set low for normal operation. HRST I Hardware Reset. Bringing HRST low resets the DS21448, setting all control bits to the all-zeros default state. MCLK I Master Clock. A 2.048MHz (±50ppm) clock source with TTL levels is applied at this pin. This clock is used internally for both clock/data recovery and for jitter attenuation. Use of a T1 1.544MHz clock source is optional (Note 1). BIS0/BIS1 I Bus Interface Select Bit 0 and 1. Used to select bus interface option. See Table 2-A for details. PBTS I Parallel Bus Type Select. When using the parallel port, set PBTS high to select Motorola bus timing; set low to select Intel bus timing. This pin controls the function of the RD (DS), ALE (AS), and WR (R/W) pins. Chip Select 1. Must be low to read or write to channel 1 of the device. CS1 is an active-low signal. Chip Select 2. Must be low to read or write to channel 2 of the device. CS2 is an active-low signal. Chip Select 3. Must be low to read or write to channel 3 of the device. CS3 is an active-low signal. CS1–CS4 I Chip Select 4. Must be low to read or write to channel 4 of the device. CS4 is an active-low signal. PBEO1–PBEO4 O PRBS Bit-Error Output. The receiver constantly searches for a 2 15 - 1 (E1) or a QRSS (T1) PRBS, depending on the ETS bit setting (CCR1.7). It remains high if it is out of synchronization with the PRBS pattern. It goes low when synchronized to the PRBS pattern. Any errors in the received pattern after synchronization cause a positive-going pulse (with same period as E1 or T1 clock) synchronous with RCLK. PRBS bit errors can also be reported to the ECR1 and ECR2 registers by setting CCR6.2 to logic 1. RCL1/LOTC1– RCL4/LOTC4 O Receive Carrier Loss/Loss-of-Transmit Clock. An output that toggles high during a receive carrier loss (CCR2.7 = 0) or toggles high if the TCLK pin has not been toggled for 5 ms ± 2ms (CCR2.7 = 1). CCR2.7 defaults to logic 0 when in hardware mode. RTIP1–RTIP4 I RRING1–RRING4 I Receive Tip and Ring. Analog inputs for clock recovery circuitry. These pins connect through a 1:1 transformer to the line. See Section 7 for details. BPCLK1–BPCLK4 O Backplane Clock. A 16.384MHz, 8.192MHz, 4.096MHz, or 2.048MHz clock output that is referenced to RCLK selectable through CCR5.7 and CCR5.6. TTIP1–TTIP4 O TRING1–TRING4 O Transmit Tip and Ring. Analog line-driver outputs. These pins connect through a step-up transformer to the line. See Section 7 for details. RPOS1–RPOS4 O Receive Positive Data. These bits are updated on the rising edge (CCR2.0 = 0) or the falling edge (CCR2.0 = 1) of RCLK with bipolar data out of the line interface. Set NRZE (CCR1.6) to 1 for NRZ applications. In NRZ mode, data is output on RPOS, and a received error (BPV, CV, or EXZ) causes a positive-going pulse synchronous with RCLK at RNEG. RNEG1–RNEG4 O Receive Negative Data. Updated on the rising edge (CCR2.0 = 0) or the falling edge (CCR2.0 = 1) of RCLK with the bipolar data out of the line interface. Set NRZE (CCR1.6) to 1 for NRZ applications. In NRZ mode, data is output on RPOS, and a received error (BPV, CV, or EXZ) causes a positive-going pulse synchronous with RCLK at RNEG. |
Similar Part No. - DS21448 |
|
Similar Description - DS21448 |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.NET |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
