Data Bus

Lines

16-Bit Write

Most Significant Byte

Least Significant Byte

Data Bus

Lines

Most Significant Byte

Least Significant Byte

8-Bit Write

16-Bit Write

Data Bus

Lines

Most Significant Byte

16-Bit Write

8-Bit Write

Least Significant Byte

TLC532AI, TLC532AM, TLC533AI, TLC533AM

LinCMOS

™ 8-BIT ANALOG-TO-DIGITAL PERIPHERALS

WITH 5 ANALOG AND 6 DUAL-PURPOSE INPUTS

SLAS070 – D2819, NOVEMBER 1983 – REVISED SEPTEMBER 1986

POST OFFICE BOX 655303

6

2 – 1

2 – 2

2 – 3

2 – 4

2 – 5

2 – 6

2 – 7

2 – 8

2 – 1

2 – 2

2 – 3

2 – 4

2 – 5

2 – 6

2 – 7

2 – 8

X

(MSB)

X

X

X

X

X

X

SC

(LSB)

X

(MSB)

X

X

X

X

X

X

SC

(LSB)

Unused Bits (X) – The MS byte bits 2 – 1 through 2 – 7 and LS byte bits 2 – 1 through 2 – 4 of the control register are not used internally.

Start Conversion (SC) – When the SC bit in the MS byte is set to a logical 1, analog-to-digital conversion on the specified analog channel

begins immediately after the completion of the control register write.

Analog Multiplex Address (A0-A3) – These four address bits are decoded by the analog multiplexer and used to select the appropriate analog

channel as shown below:

Hexadecimal Address (A3 = MSB)

Channel Select

0A0

1

REF + (A1)

2-5

A2-A5

6-9 (not used)

A-F

A10-A15

Figure 2. Word Format and Content for Control Register 2-Byte Write

2 – 1

2 – 2

2 – 3

2 – 4

2 – 5

2 – 6

2 – 7

2 – 8

2 – 1

2 – 2

2 – 3

2 – 4

2 – 5

2 – 6

2 – 7

2 – 8

EOC

(MSB)

0

0

0

0

0

0

0

(LSB)

R7

(MSB)

R6

R5

R4

R3

R2

R1

R0

(LSB)

A/D Status (EOC) – The A/D status end-of-conversion (EOC) bit is set whenever an analog-to-digital conversion is successfully completed

by the A/D converter. The status bit is cleared by a 16-bit write from the microprocessor to the control register. The remainder of the bits

in the MS byte of the analog conversion data register are always reset to logical 0 to simplify microprocessor interrogation of the A/D

converter status.

A/D Result (R0-R7) – The LS byte of the analog conversion data register contains the result of the analog-to-digita

Figure 3. Word Format and Content for Analog Conversion Data Register 1-Byte and 2-Byte Read

2 – 1

2 – 2

2 – 3

2 – 4

2 – 5

2 – 6

2 – 7

2 – 8

2 – 1

2 – 2

2 – 3

2 – 4

2 – 5

2 – 6

2 – 7

2 – 8

A15/D6

(MSB)

A14

/D5

A13

/D4

A12

/D3

A11

/D2

A10

/D1

A3

A2

(LSB)

A1

(MSB)

A0

X

X

X

X

X

X

(LSB)

Shared Digital Port (A10/D1-A15/D6) – The voltage present on these pins is interpreted as a digital signal, and the corresponding states

are read from these bits. A digital value is given for each pin even if some or all of these pins are being used as analog inputs.

Analog Multiplexer Address (A0-A3) – The address of the selected analog channel presently addressed is given by these bits.

Unused Bits (X) – LS byte bits 2 – 3 through 2 – 8 of the digital data register are not used.

Figure 4. Word Format And Content For Digital Data Register 1-Byte and 2-Byte Read