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TLC1518IPW Datasheet(PDF) 4 Page - Texas Instruments

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Part # TLC1518IPW
Description  5-V, 10-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TLC1518IPW Datasheet(HTML) 4 Page - Texas Instruments

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TLC1514, TLC1518
5-V, 10-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER,
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN
SLAS252 – DECEMBER 1999
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions (Continued)
TERMINAL
NAME
NO.
I/O
DESCRIPTION
NAME
TLC1514
TLC1518
SDO
1
1
O
The 3-state serial output for the A/D conversion result. SDO is kept in the high-impedance state
when CS is high and after the CS falling edge and until the MSB (D15) is presented. The output
format is MSB (D15) first.
When FS is not used (FS = 1 at the falling edge of CS), the MSB (D15) is presented to the SDO
pin after the CS falling edge, and successive data are available at the rising edge of SCLK.
When FS is used (FS = 0 at the falling edge of CS), the MSB (D15) is presented to SDO after the
falling edge of CS and FS = 0 is detected. Successive data are available at the falling edge of SCLK.
(This is typically used with an active FS from a DSP.)
For conversion and FIFO read cycles, the first 10 bits are the result from the previous conversion
(data) followed by 6 don’t cares. The first four bits from SDO for CFR read cycles should be ignored.
The register content is in the last 12 bits. SDO is 3 stated after the 16th bit.
REFM
14
18
I
External reference input or internal reference decoupling.
REFP
15
19
I
External reference input or internal reference decoupling. (Shunt capacitors of 10
µF and 0.1 µF
between REFP and REFM.) The maximum input voltage range is determined by the difference
between the voltage applied to this terminal and the REFM terminal when an external reference
is used.
VCC
5
5
I
Positive supply voltage
detailed description
analog inputs and internal test voltages
The 4/8 analog inputs and three internal test inputs are selected by the analog multiplexer depending on the
command entered. The input multiplexer is a break-before-make type to reduce input-to-input noise injection
resulting from channel switching.
pseudo-differential/single-ended input
All analog inputs can be programmed as single-ended or pseudo-differential mode. Pseudo-differential mode
is enabled by setting CFR.D7 – 1. Only three analog input channels (or seven channels for the TLC1518) are
available for TLC1514 since one input (A1 for TLC1514 or A2 for TLC1518) is used as the MINUS input when
pseudo-differential mode is used. The minus input pin can have a maximum
"0.2 V ripple. This is normally used
for ground noise rejection.
converter
The TLC1514/18 uses a 10-bit successive approximation ADC utilizing a charge redistribution DAC. Figure 1
shows a simplified version of the DAC.
The sampling capacitor acquires the signal on Ain during the sampling period. When the conversion process
starts, the SAR control logic and charge redistribution DAC are used to add and subtract fixed amounts of charge
from the sampling capacitor to bring the comparator into a balanced condition. When the comparator is
balanced, the conversion is complete and the ADC output code is generated.


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