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TLC2933IPWLE Datasheet(PDF) 6 Page - Texas Instruments |
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TLC2933IPWLE Datasheet(HTML) 6 Page - Texas Instruments |
6 / 24 page TLC2933 HIGHPERFORMANCE PHASELOCKED LOOP SLAS136B − APRIL 1996 − REVISED JANUARY 2002 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 operating characteristics over recommended operating free-air temperature range, VDD = 3 V (unless otherwise noted) VCO section PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fosc Operating oscillation frequency RBIAS = 2.4 kΩ, VCO IN = 1/2 VDD 38 48 55 MHz ts(fosc) Time to stable oscillation (see Note 8) Measured from VCO INHIBIT ↓ 10 µs tr Rise time, VCO OUT ↑ CL = 15 pF, See Figure 3 3.3 10 ns tf Fall time, VCO OUT ↓ CL = 15 pF, See Figure 3 2 8 ns Duty cycle at VCO OUT RBIAS = 2.4 kΩ, VCO IN = 1/2 VDD 45% 50% 55% α(fosc) Temperature coefficient of oscillation frequency RBIAS = 2.4 kΩ, VCO IN = 1/2 VDD, TA = −20°C to 75°C 0.03 %/ °C kSVS(fosc) Supply voltage coefficient of oscillation frequency RBIAS = 2.4 kΩ, VCO IN = 1.5 V, VDD = 2.85 V to 3.15 V 0.04 %/mV Jitter absolute (see Note 9) RBIAS = 2.4 kΩ 100 ps NOTES: 8. The time period to stabilize the VCO oscillation frequency after the VCO INHIBIT terminal is changed to a low level. 9. Jitter performance is highly dependent on circuit layout and external device characteristics. The jitter specification was made with a carefully designed printed circuit board (PCB) with no device socket. PFD section PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fmax Maximum operating frequency 30 MHz tPLZ Disable time, PFD INHIBIT ↑ to PFD OUT Hi-Z 20 40 ns tPHZ Disable time, PFD INHIBIT ↑ to PFD OUT Hi-Z See Figures 4 and 5 and Table 3 18 40 ns tPZL Enable time, PFD INHIBIT ↓ to PFD OUT low See Figures 4 and 5 and Table 3 4.1 18 ns tPZH Enable time, PFD INHIBIT ↓ to PFD OUT high 4.8 18 ns tr Rise time, PFD OUT ↑ CL = 15 pF, See Figure 4 3.1 9 ns tf Fall time, PFD OUT ↓ CL = 15 pF, See Figure 4 1.5 9 ns |
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