TLC2933A

HIGH PERFORMANCE PHASE LOCKED LOOP

SLES149 − OCTOBER 2005

6

TI.COM

PFD section

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VOH

High level output voltage

IOH = –2 mA

2.4

V

VOL

Low level output voltage

IOL = 2 mA

0.3

V

IOZ

High impedance state output current

PFD inhibit = high, VO = VDD or GND

±1

µA

VIH

High level input voltage at Fin−A, Fin−B

2.1

V

VIL

Low level input voltage at Fin−A, Fin−B

0.5

V

VTH

Input threshold voltage at PFD inhibit

0.9

1.5

2.1

CIN

Input capacitance at Fin−A, Fin−B

5.6

pF

ZIN

Input impedance at Fin−A, Fin−B

10

M

Ω

IDD(Z)

High impedance state PFD supply current

See Note 6

1

µA

IDD(PFD)

PFD supply current

See Note 7

3

mA

NOTES:

6. The current into LOGIC VDD when FIN−A and FIN−B = ground, PFD INHIBIT = VDD, PFD OUT open, and VCO OUT is inhibited.

7. The current into LOGIC VDD when FIN−A = 1 MHz and FIN−B = 1 MHz (VI(PP) = 3 V, rectangular wave), PFD INHIBIT = GND, PFD

OUT open, and VCO OUT is inhibited.

VCO section

Parameter

TEST CONDITIONS

MIN

TYP

MAX

UNIT

fOSC

Operation oscillation frequency

RBIAS = 3.3 kΩ, VCO IN = 1/2 VDD

32

47

63

MHz

fSTB

Time to stable oscillation (see Note 8)

10

µs

tr

Rise time

CL = 15 pF

8.6

14

ns

tf

Fall time

CL = 15 pF

7.1

12

ns

Duty cycle at VCO OUT

RBIAS = 3.3 kΩ, VCO IN = 1/2 VDD

45%

50%

55%

α (fOSC) Temperature coefficient of oscillation

frequency

VCO IN = 1/2 VDD,

TA = –20°C to 75°C

–0.21

%/

°C

kSVS

(fosc)

Supply voltage coefficient of oscillation

frequency

VCO IN = 1/2 VDD,

VDD = 4.75 V to 5.25 V

0.002

%/mV

Jitter absolute (see Note 9)

PLL jitter, N = 128

262

ps

NOTES:

8. The time period to the stable VCO oscillation frequency after the VCO INHIBIT terminal is changed to a low level.

9. Jitter performance is highly dependent on circuit layout and external device characteristics. The jitter specification was made with

a carefully deigned PCB with no device socket.

PFD section

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

fmax

Maximum operation frequency

32

MH

tPLZ

PFD output disable time from low level

22

50

ns

tPHZ

PFD output disable time from high level

21

50

ns

tPZL

PFD output enable time to low level

6.5

30

ns

tPZH

PFD output enable time to high level

7

30

ns

tr

Rise time

CL = 15 pF

3.4

10

ns

tf

Fall time

CL = 15 pF

1.9

10

ns