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TLC2942IDBR Datasheet(PDF) 1 Page - Texas Instruments |
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TLC2942IDBR Datasheet(HTML) 1 Page - Texas Instruments |
1 / 29 page TLC2942 HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D Dual TLC2932 by Multichip Module (MCM) Technology D Voltage-Controlled Oscillator (VCO) Section: – Complete Oscillator Using Only One External Bias Resistor (RBIAS) – Recommended Lock Frequency Range: 22 MHz to 50 MHz (VDD = 5 V ±5%, TA = –20°C to 75°C, ×1 Output) 11 MHz to 25 MHz (VDD = 5 V ±5%, TA = –20°C to 75°C, ×1/2 Output) – Output Frequency... ×1 and ×1/2 Selectable D Includes a High-Speed Edge-Triggered Phase Frequency Detector (PFD) With Internal Charge Pump D Independent VCO, PFD Power-Down Mode description The TLC2942 is a multichip module product that uses two TLC2932 chips. The TLC2932 chip is composed of a voltage-controlled oscillator and an edge-triggered phase frequency detector. The oscillation frequency range of each VCO is set by an external bias resistor (RBIAS) and each VCO output can be a ×1 or ×1/2 output frequency. Each high speed PFD with internal charge pump detects the phase difference between the reference frequency input and signal frequency input from the external counter. The VCO and the PFD have inhibit functions that can be used as a power-down mode. The high-speed and stable oscillation capability of the TLC2932 makes the TLC2942 suitable for use in dual high-performance phase-locked loop (PLL) systems. AVAILABLE OPTIONS PACKAGE TA SMALL OUTLINE (DB) –20 °C to 75°C TLC2942IDB Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright © 1997, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 LOGIC VDD1 SELECT1 VCO OUT1 FIN–A1 FIN–B1 PFD OUT1 LOGIC GND1 GND NC NC NC GND LOGIC VDD2 SELECT2 VCO OUT2 FIN–A2 FIN–B2 PFD OUT2 LOGIC GND2 VCO VDD1 BIAS1 VCOIN1 VCO GND1 VCOINHIBIT1 PFD INHIBIT1 NC GND NC NC NC GND VCO VDD2 BIAS2 VCOIN2 VCO GND2 VCOINHIBIT2 PFD INHIBIT2 NC DB PACKAGE (TOP VIEW) NC – No internal connection |
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