PC66 SDRAM MODULE

KMM366S403CTL

REV. 3 Mar. '98

1. Parameters depend on programmed CAS latency.

2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.

3. Assumed input rise and fall time (tr & tf) = 1ns.

If tr & tf is longer than 1ns, transient time compensation should be considered,

i.e., [(tr + tf)/2-1]ns should be added to the parameter.

Notes :

REFER TO THE INDIVIDUAL COMPONENET, NOT THE WHOLE MODULE.

Parameter

Symbol

-0

Unit

Note

Min

Max

CLK cycle time

CAS latency=3

10

1000

ns

1

CAS latency=2

13

CLK to valid

output delay

CAS latency=3

7

ns

1,2

CAS latency=2

8

Output data

hold time

CAS latency=3

3

ns

2

CAS latency=2

3

CLK high pulse width

3.5

ns

3

CLK low pulse width

3.5

ns

3

Input setup time

2.5

ns

3

Input hold time

1

ns

3

CLK to output in Low-Z

1

ns

2

CLK to output

in Hi-Z

CAS latency=3

7

ns

CAS latency=2

8