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HV311 Datasheet(PDF) 4 Page - Supertex, Inc |
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HV311 Datasheet(HTML) 4 Page - Supertex, Inc |
4 / 17 page 4 HV311 ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com Functional Block Diagram The HV311 provides control over the power supply cur- rent on systems where circuit cards are inserted into live backplanes. Such systems can frequently be found in the telecom, data networking and computing industry. The de- vice provides means of limiting the power supply current af- ter contact with the live backplane is made, thereby protect- ing card and backplane connectors and reducing the voltage disturbance on the backplane’s power supply. Additional protection is provided in the form of a circuit breaker function and a start-up time limiter, both for protection of the external MOSFET and the system as a whole. Start-up Sequence After first contact is made with the backplane, the HV311 tries to establish an internal bias supply of 10V. During this time, GATE and RAMP are positively held low by circuitry that can operate with partial supply voltage, and PWRGD is in a high impedance state. Whentheinternalbiassupplyisinregulation,theundervoltage (UV) and overvoltage (OV) comparators start monitoring the external power supply. External resistor dividers at UV and OV pin set the window for normal operating supply voltage. These may be two individual dividers, or a single divider with two taps, as shown in the application diagrams. Once the power supply voltage is within normal operating range, a 10μA internal source turns on to charge an external capacitor at the RAMP pin. The voltage at the GATE output follows the RAMP pin voltage with an offset of about 2.5V for control of the external MOSFET. Power supply current starts to flow once the GATE voltage reaches the MOSFET threshold voltage, which is typically in the 2.0 to 4.0V range. The current sense amplifier at the SENSE pin reduces the RAMP charging current in propor- tion to the supply current, thereby slowing the voltage rise at RAMP, and thus the rise of the GATE voltage. At a sense voltage of 50mV the RAMP current is reduced to zero, and the RAMP and GATE voltages stop rising, thereby prevent- ing a further rise in the power supply current. V BG C C C UV OV Logic Regulator & POR VIN PWRGD ~9.8V RAMP 2V BG gm SENSE 10A Transconductor D I S A B L E P U L L H I G H V REG 1 : 2 buffer mirror GATE 5k 5kΩ Latch High Sleep Clamp Mechanism Transconductor UVLO VEE Functional Description |
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