10

HV311

Application Circuit 5

Application Circuit 6

Note:

A capacitor may be needed to slow PWRGD dv/dt if gate oscillations are observed when V

Note:

A capacitor may be needed to slow PWRGD dv/dt if gate oscillations are observed when V

-48V

R4

12.5mΩ

R1

487kΩ

R2

6.81kΩ

R3

9.76kΩ

Q1

IRF530

C

LOAD

+5.0V

8

3

2

5

7

4

COM

1

GND

C1

10nF

C2

6

DC/DC

PWM

CONVERTER

VDD

UV

OV

VEE

SENSE GATE

RAMP

HV311

PWRGD

ENABLE

-48V

R5

12.5mΩ

R1

475kΩ

R2

16.2kΩ

R3

511kΩ

Q1

IRF530

C

LOAD

+5.0V

8

3

2

5

7

4

COM

1

GND

C1

10nF

C2

R4

10kΩ

DC/DC

PWM

CONVERTER

6

VDD

UV

OV

VEE

SENSE GATE

RAMP

HV311

PWRGD

ENABLE

Filtering Voltage Spikes on Input Supply

In some systems over voltage spikes of very short duration may exist. For these systems a small capacitor may be added

from the OV pin to the VEE pin to filter the voltage spikes.

Unfortunately this will also cause some delay in responding to UV conditions. If this UV delay is not acceptable, then sepa-

rate resistor dividers can be provided for OV and UV with a capacitor connected from OV pin to the VEE pin.