 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
TDA6650 Datasheet(PDF) 11 Page - NXP Semiconductors |
|
||||||||||||||||||||||||||||||
TDA6650 Datasheet(HTML) 11 Page - NXP Semiconductors |
|
|
11 / 55 page  2004 Mar 22 11 Philips Semiconductors Product specification 5 V mixer/oscillator and low noise PLL synthesizer for hybrid terrestrial tuner (digital and analog) TDA6650TT; TDA6651TT 8.1.2 XTOUT OUTPUT BUFFER AND MODE SETTING The crystal frequency can be sent to pin XTOUT and used in the application, for example to drive the clock input of a digital demodulator, saving a quartz crystal in the bill of material. To output fxtal, it is necessary to set T[2:0] to 001. If the output signal on this pin is not used, it is recommended to disable it, by setting T[2:0] to 000. This pin is also used to output 1/2fdiv and fcomp in a test mode. At Power-on, the XTOUT output buffer is set to on, supplying the fxtal signal. The relation between the signal on pin XTOUT and the setting of theT[2:0] bits is given in Table 6. Table 6 XTOUT buffer status and test modes Notes 1. Automatic Loop Bandwidth Control (ALBC) is disabled at Power-on reset. After Power-on reset this feature is enabled by setting T[2:0] = 011. To disable again the ALBC, set T[2:0] = 011 again. This test mode acts like a toggle switch, which means each time it is set the status of the ALBC changes. To toggle the ALBC, two consecutive Control byte 1s (CB1), should be sent: one byte with T[2:0] = 011 indicating that ALBC will be switched on or off and one byte programming the test mode to be selected (see Table 23, example of I2C-bus sequence). 2. This is the default mode at Power-on reset. This mode disables the tuning voltage. 8.1.3 STEP FREQUENCY SETTING The step frequency is set by three bits, giving five steps to cope with different application requirements. The reference divider ratio is automatically set depending on bits R2, R1 and R0. The phase detector works at either 4, 2 or 1 MHz. Table 7 shows the step frequencies and corresponding reference divider ratios. When the value of bits R2, R1 and R0 are changed, it is necessary to re-send the data bytes DB1 and DB2. Table 7 Reference divider ratio select bits T2 T1 T0 PIN XTOUT MODE 0 0 0 disabled normal mode with XTOUT buffer off 001 fxtal (4 MHz) normal mode with XTOUT buffer on 010 1/2fdiv charge pump off 011 fxtal (4 MHz) switch ALBC on or off (note 1) 100 fcomp test mode 101 1/2fdiv test mode 110 fxtal (4 MHz) charge pump sinking current (note 2) 1 1 1 disabled charge pump sourcing current R2 R1 R0 REFERENCE DIVIDER RATIO FREQUENCY COMPARISON FREQUENCY STEP 0 0 0 2 2 MHz 62.5 kHz 0 0 1 1 4 MHz 142.86 kHz 0 1 0 1 4 MHz 166.67 kHz 0 1 1 4 1 MHz 50 kHz 1 0 0 1 4 MHz 125 kHz 101 −− reserved 110 −− reserved 111 −− reserved |
Similar Part No. - TDA6650 |
|
Similar Description - TDA6650 |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.NET |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
