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UC3826 Datasheet(PDF) 6 Page - Texas Instruments

Part # UC3826
Description  Secondary Side Average Current Mode Controller
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

UC3826 Datasheet(HTML) 6 Page - Texas Instruments

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UC1826
UC2826
UC3826
Figure 1. Oscillator Block with External Connections
PWM Oscillator: The chip has two pins that set RC time
constants. The resistor and capacitor tied to RAMP cre-
ate the ramp used as the input to the PWM comparator.
When the output pin OUT is high, RAMP charges until it
passes the PWM comparator threshold. The output is
then driven low and RAMP is discharged. The resistors
and capacitor on the OSC pin are used to set the PWM
operating frequency and its maximum duty cycle.
The oscillator block diagram with external wiring is shown
in Figure 1. OSC has a capacitor (CT) to ground and two
resistors in series (RT and RDEAD) to VREF. The total re-
sistance of RT and RDEAD divided by VREF - VOSC sets
the exponential charge current. The oscillator charges
from 1.2V to a 3.4V threshold with an RC time delay of 2
• CT • (RDEAD +RT). After exceeding this threshold, the
RS flip-flop is set driving CLKSYN high and RDEAD low
which discharges CT. At this time an open collector tran-
sistor is turned on and discharges CT capacitor through
RDEAD with a RC time delay of 2
• CT • RDEAD. The os-
cillator and ramp waveforms are shown in Figure 2.
Equations to attain frequency and maximum duty cycle
are listed under the OSC pin description.
As shown in Figure 3, several oscillators are synchro-
nized to the highest free running frequency by connect-
ing 100pF capacitors in series with each CLKSYN pin
and connecting the other side of the capacitors together
forming the CLKSYN bus. The CLKSYN bus is then
pulled down to ground with a resistance of approximately
10k. Referring to Figure 1, the synchronization threshold
is 1.4V. The oscillator blanks any synchronization pulse
that occurs when OSC is below 2.5V. This allows units,
once they discharge below 2.5V, to continue through the
current
discharge
and
subsequent
charge
cycles
whether or not other units on the CLKSYN bus are still
synchronizing. This requires the frequency of all free run-
ning oscillators to be within 40% of each other to guaran-
tee synchronization.
Grounds, Voltage Sensing and Current Sensing: The
voltage is sensed directly at the load. Proper load sharing
requires the same sensed voltage for each power supply
connected
in
parallel. Referring
to
Figure
4,
the
CIRCUIT DESCRIPTION:
OSC
OUT
CLKSYN
RAMP
CAO
3.0-
1.0
Figure 2. Oscillator and PWM Output Waveform
UDG-95014-1


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