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TLC5929PWP Datasheet(PDF) 11 Page - Texas Instruments |
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TLC5929PWP Datasheet(HTML) 11 Page - Texas Instruments |
11 / 43 page TLC5929 www.ti.com SBVS159B – APRIL 2011 – REVISED JULY 2012 PIN DESCRIPTIONS PIN NAME DBQ/PWP RGE I/O DESCRIPTION Blank all outputs. When BLANK is high, all constant-current outputs (OUT0 to OUT15) are BLANK 21 18 I forced off. When BLANK is low, all constant-current outputs are controlled by the on/off control data in the data latch. GND 1 22 — Ground Maximum current programming terminal. A resistor connected between IREF and GND sets the maximum current for every constant-current output. When this terminal is directly IREF 23 20 I/O connected to GND, all outputs are forced off. The external resistor should be placed close to the device and must be in the range of 1.32 k Ω to 66.0 kΩ. Data latch. The rising edge of LAT latches the data from the common shift register into the output on/off data latch. At the same time, the data in the common shift register are replaced LAT 4 1 I with SID, which is selected by SIDLD. See the Output On/Off Data Latch section and Status Information Data (SID) section for more details. OUT0 5 2 O OUT1 6 3 O OUT2 7 4 O OUT3 8 5 O OUT4 9 6 O OUT5 10 7 O OUT6 11 8 O OUT7 12 9 O Constant-current sink outputs. Multiple outputs can be configured in parallel to increase the constant-current capability. Different voltages can be applied to each output. OUT8 13 10 O OUT9 14 11 O OUT10 15 12 O OUT11 16 13 O OUT12 17 14 O OUT13 18 15 O OUT14 19 16 O OUT15 20 17 O Serial data shift clock. Data present on SIN are shifted to the LSB of the 17-bit shift register SCLK 3 24 I with the SCLK rising edge. Data in the shift register are shifted toward the MSB at each SCLK rising edge. The MSB data of the common shift register appear on SOUT. Serial data input for the 17-bit common shift register. When SIN is high, a '1' is written to the SIN 2 23 I LSB of the common shift register at the rising edge of SCLK. Serial data output of the 17-bit common shift register. SOUT is connected to the MSB of the SOUT 22 19 O 17-bit shift register. Data are clocked out at the rising edge of SCLK. VCC 24 21 — Power-supply voltage Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Link(s): TLC5929 |
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