TLK3104SA

QUAD 3.125 Gbps SERIAL TRANSCEIVER

SCAS651B-− AUGUST 2000 − REVISED SEPTEMBER 2001

8

POST OFFICE BOX 655303

parallel interface data (continued)

In SERDES mode, the receive data bus for each channel outputs 10-bit wide 8-B/10-B encoded data on

RDx[0..9]. The 8-B/10-B encoded data input to the differential high-speed serial receive pins is deserialized with

the first bit (bit 0) output on RDx0 and the last bit (bit 9) output on RDx9. Data is output relative to both the rising

and falling edge of the receive clock.

Table 3. Parallel Data Modes

CODE

PARALLEL INTERFACE DATA OPERATION

Low

SERDES mode. On-chip 8-B/10-B encoder/ decoder is disabled. Data on TDx[0..9] and RDx[0..9] is treated as 8-B/10-B encoded

data.

High

Transceiver mode. Enables 8-B/10-B encode/decode for each channel. Data TDx[0..7] and RDx[0..7] is treated as uncoded data.

TDx8 is used as the K-character generator control. RDx8 is the K-character indicator to the host device. Data on TDx9 is ignored. RDx9

asserts high on either a disparity or code error.

In transceiver mode, the transmit data bus for each channel accepts 8-bit wide parallel data at the TDx[0..7] pins.

Data is sampled on the rising and falling edge of the transmit clock as shown in Figure 4. The data is first aligned

to the reference clock (RFCP/RFCN), then 8-B/10-B encoded and passed to the serializer. The generation of

K-characters on each channel is controlled by TDx8(KGEN). When KGEN is asserted along with the 8 bits of

data TDx[0..7], the appropriate 8-B/10-B K-character is transmitted.

In transceiver mode, the receive data bus for each channel outputs 8-bit wide parallel data on RDx[0..7].

Reception of K-characters is reported on RDx8 (KFLAG). When KFLAG is asserted, the 8 bits of data on

RDx[0..7] should be interpreted as a K-character. If an error is uncovered in decoding the data, KFLAG and

RDx9 (RX_ER) are asserted high and all 1s (0xFF) are placed on the receive data bus for that channel.

transmit data bus timing

For each channel, the transmitter portion of the TLK3104SA latches the data on transmit data bus TDx[0..9] on

both the rising and falling edges of the transmit data clock, as shown in Figure 4. Depending on the state of

PSYNC pin the transmit data clock is either TCA (channel sync mode) or the individual transmit channel clocks,

TCA−TCD (independent channel mode). When in the channel sync mode, signals on TCB, TCC, and TCD are

ignored.

tsu

th

th

tsu

Data

Data

TCA, TCB,

TCC, TCD

TDx[0...9]

Figure 4. Transmit Interface Timing

transmission latency

For each channel, the data transmission latency of the TLK3104SA is defined as the delay from the rising or

falling edge of the selected transmit clock when valid data is on the transmit data pins to the serial transmission

There are approximately 20 bit times required for the 8-B/10-B encoder.