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TLK1201ARCPRG4 Datasheet(PDF) 4 Page - Texas Instruments |
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TLK1201ARCPRG4 Datasheet(HTML) 4 Page - Texas Instruments |
4 / 24 page www.ti.com TLK1201ARCP, TLK1201AIRCP ETHERNET TRANSCEIVERS SLLS580D – FEBRUARY 2004 – REVISED SEPTEMBER 2007 Terminal Functions (continued) TERMINAL I/O DESCRIPTION NAME NO. RD0–RD9 45, 44, O Receive data. When in TBI mode (MODESEL = low), these outputs carry 10-bit parallel data 43, 41, output from the transceiver to the protocol layer. The data is referenced to terminals RBC0 and 40, 39, RBC1, depending on the receive clock mode selected. RD0 is the first bit received. When in the 38, 36, DDR mode (MODESEL = high), only RD0–RD4 are valid. RD5–RD9 are held low. The 5-bit 35, 34 parallel data is clocked out of the transceiver on the rising edge of RBC0. REFCLK 22 I Reference clock. REFCLK is an external input clock that synchronizes the receiver and transmitter interface (60 MHz to 130 MHz). The transmitter uses this clock to register the input data (TD0–TD9) for serialization. In the TBI mode that data is registered on the rising edge of REFCLK. In the DDR mode, the data is registered on both the rising and falling edges of REFCLK with the most significant bits aligned on the rising edge of REFCLK. RXP 54 PECL I Differential input receive. RXP and RXN together are the differential serial input interface from a RXN 52 copper or an optical I/F module. SYNCEN 24 I Synchronous function enable. When SYNCEN is high, the internal synchronization function is P/U(2) activated. When this function is activated, the transceiver detects the K28.5 comma character (0011111 negative beginning disparity) in the serial data stream and realigns data on byte boundaries if required. When SYNCEN is low, serial input data is unframed in RD0–RD9. SYNC/PASS 47 O Synchronous detect. The SYNC output is asserted high upon detection of the comma pattern in the serial data path. SYNC pulses are output only when SYNCEN is activated (asserted high). In PRBS test mode (PRBSEN = high), SYNC/PASS outputs the status of the PRBS test results (high = pass). TD0–TD9 2-4, 6-9, I Transmit data. When in the TBI mode (MODESEL = low) these inputs carry 10-bit parallel data 11-13 output from a protocol device to the transceiver for serialization and transmission. This 10-bit parallel data is clocked into the transceiver on the rising edge of REFCLK and transmitted as a serial stream with TD0 sent as the first bit. When in the DDR mode (MODESEL = high) only TD0–TD4 are valid. The 5-bit parallel data is clocked into the transceiver on the rising and falling edge of REFCLK and transmitted as a serial stream with TD0 sent as the first bit. TXP 62 PECL Differential output transmit. TXP and TXN are differential serial outputs that interface to a copper TXN 61 O or an optical I/F module. TXP and TXN are put in a high-impedance state when LOOPEN is high and are active when LOOPEN is low. TEST ENABLE 28 I When this terminal is low, the device is disabled for Iddq testing. RD0–RD9, RBCn, TXP, and P/U(3) TXN are high impedance. The pullup and pulldown resistors on any input are disabled. When ENABLE is high, the device operates normally. JTDI 48 I Test data input. IEEE1149.1 (JTAG) P/U(3) JTDO 27 O Test data output. IEEE1149.1 (JTAG) JTMS 55 I Test mode select. IEEE1149.1 (JTAG) P/U(3) JTRSTN 56 I Reset signal. IEEE1149.1 (JTAG) P/U(3) LOOPEN 19 I Loop enable. When LOOPEN is high (active), the internal loop-back path is activated. The P/D(4) transmitted serial data is directly routed to the inputs of the receiver. This provides a self-test capability in conjunction with the protocol device. The TXP and TXN outputs are held in a high-impedance state during the loop-back test. LOOPEN is held low during standard operational state with external serial outputs and inputs active. PRBSEN 16 I PRBS enable. When PRBSEN is high, the PRBS generation circuitry is enabled. The PRBS P/D(4) verification circuit in the receive side is also enabled. A PRBS signal can be fed to the receive inputs and checked for errors, that are reported by the SYNC/PASS terminal indicating low. TCK 49 I Test clock. IEEE1149.1 (JTAG) TESTEN 17 I Manufacturing test terminal P/D(4) (2) P/U = Internal pullup (3) P/U = Internal pullup (4) P/D = Internal pulldown 4 Submit Documentation Feedback Copyright © 2004–2007, Texas Instruments Incorporated Product Folder Link(s): TLK1201ARCP TLK1201AIRCP |
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