AN4149 datasheet(8/19 Pages) FAIRCHILD

Part #	AN4149

Description	Design Guidelines

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Manufacturer	FAIRCHILD [Fairchild Semiconductor]

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AN4149

APPLICATION NOTE

8

[STEP-11] Determine the output capacitors considering

the voltage and current ripple.

The ripple current of the n-th output capacitor (Co(n)) is

obtained as

where Io(n) is the load current of the n-th output and ID(n)

rms

is specified in equation (23). The ripple current should be

smaller than the maximum ripple current specification of the

capacitor. The voltage ripple on the n-th output is given by

where Co(n) is the capacitance, Rc(n) is the effective series

resistance (ESR) of the n-th output capacitor, KL(n), Dmax and

Ids

peak are specified in equations (2), (6) and (8) respectively,

VRO is specified in STEP-3, Io(n) and Vo(n) are the load

current and output voltage of the n-th output, respectively

and VF(n) is the diode (DR(n)) forward voltage drop.

Sometimes it is impossible to meet the ripple specification

with a single output capacitor due to the high ESR of the

electrolytic capacitor. In those cases, additional L-C filter

stages (post filter) can be used to reduce the ripple on the

output.

[STEP-12] Design the synchronization network.

KA5Q-series employs a quasi resonant switching technique

to minimize the switching noise as well as switching loss. In

this technique, a capacitor (Cr) is added between the

MOSFET drain and source as shown in Figure 11. The basic

waveforms of a quasi-resonant converter are shown in Figure

12. The external capacitor lowers the rising slope of drain

voltage, which reduces the EMI caused by the MOSFET

turn-off. To minimize the MOSFET switching loss, the

MOSFET should be turned on when the drain voltage

reaches its minimum value as shown in Figure 12.

The optimum MOSFET turn-on time is indirectly detected

by monitoring the Vcc winding voltage as shown in Figure

11 and 12. The output of the sync detect comparator (CO)

becomes high when the sync voltage (Vsync) exceeds 4.6V

and low when the Vsync reduces below 2.6V. The MOSFET is

turned on at the falling edge of the sync detect comparator

output (CO).

Figure. 11 Synchronization Circuit

The peak value of the sync signal is determined by the

voltage divider network R

SY1 and RSY2 as

Choose the voltage divider R

SY1 and RSY2 so that the peak

value of sync voltage (Vsync

pk) is lower than the OVP

threshold voltage (12V) in order to avoid triggering OVP in

normal operation. Typically, Vsync

pk is set to 8~10V.

To synchronize the Vsync with the MOSFET drain voltage,

choose the sync capacitor (CSY) so that TF is same as TQ as

shown in Figure 12. TF and TQ are given, respectively, as

where Lm is the primary side inductance of the transformer,

Ns and Na are the number of turns for the output winding and

Vcc winding, respectively and Ceo is the effective MOSFET

output capacitance (Coss+Cr).

I

cap n

()

rms

I

Dn

()

rms

()

2

I

on

()

2

–

=

(26)

∆V

on

()

I

on

()Dmax

C

on

()fs

min

--------------------------

I

ds

peak

V

RORCn

()KLn

()

V

on

()

V

Fn

()

+

()

----------------------------------------------------------- (27)

+

=

Vcc

C

a

D

a

GND

C

r

Drain

I

ds

R

cc

R

SY1

R

SY2

Sync

V

o1

C

SY

+

V

ds

-

N

s1

N

p

L

m

+

-

CO

4.6/2.6V

D

SY

N

a

KA5Q-series

V

sync

Sync comparator

V

sync

pk

R

SY2

R

SY1

R

SY2

+

---------------------------------- V

cc

⋅

=

28

()

T

F

π

L

m

C

eo

⋅

=

(29)

T

Q

R

SY2

C

SY

V

cc

2.6

---------

R

SY2

R

SY1

R

SY2

+

----------------------------------

⋅

⎝⎠

⎛⎞

ln

⋅⋅

=

(30)

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