©2002 Fairchild Semiconductor Corporation

Application Note 7502 Rev. A1

AN-7502

Power MOSFET Switching Waveforms:

A New Insight

The examination of power MOSFET voltage and current

waveforms during switching transitions reveals that the

device characterization now practiced by industry is inade-

quate. In this Note, device waveforms are explained by con-

sidering the interaction of a vertical JFET driven in cascode

from a lateral MOSFET in combination with the interelec-

trode capacitances. Particular attention is given to the

drain-voltage waveform and its dual-slope nature. The

three terminal capacitances now published by the industry

are shown to be valid only for zero drain current. For cases

where the gate drive is a voltage step generator with inter-

nal fixed resistance, the drain voltage characteristics are

inferred from the gate current drive behavior and compared

to observed waveforms. The nature of the “asymmetric

switching times” is explained.

A waveform family is proposed as a more descriptive and

accurate method of characterization. This new format is a

plot of drain voltage and gate voltage versus normalized

time. A family of curves is presented for a constant load

transitions is a constant current with voltage compliance

limits of 0 and 10 volts. Time is normalized by the value of

gate driving current. The normalization shows excellent

agreement with data over five orders of magnitude, and is

bounded on one extreme by gate propagation effects and

on the other by transition time self-heating (typically tens of

nanoseconds to hundreds of microseconds).

Device Models

The keystone of an understanding of power MOSFET

switching performance is the realization that the active

device is bimodal and must be described using a model that

accounts for the dual nature. Buried in today’s power MOS-

FET devices is the equivalent of a depletion layer JFET that

contributes significantly to switching speed. Figure 1 is a

cross-sectional view of a typical power MOSFET, with MOS-

FET/JFET symbols superimposed on the structure.

Figure 2 is obtained by taking the lateral MOS and vertical

JFET from this conception and adding all the possible node-

to-node capacitances. Computed values of the six capaci-

tances for a typical device structure suggest that device

behavior may be adequately modeled using only three

capacitors in the manner of Figure 3. This is the model to be

employed for analysis and study.

FIGURE 1. CROSS-SECTION VIEW OF MOSFET SHOWING

EQUIVALENT MOS TRANSISTOR AND JFET

FIGURE 2.

MOS TRANSISTOR WITH CASCODE-CONNECTED

JFET AND ALL CAPACITORS

FIGURE 3.

FIGURE 2 SIMPLIFIED

Gate Drive: Constant Voltage or

Constant Current

Before moving on to the study of the equivalent circuit states

of the model, a gate-drive forcing function which is easy to

represent, relates to reality, and best illustrates device

behavior must be chosen. The choice may be immediately

narrowed to two:

(1) An instantaneous step voltage with internal resistance R,

Figure 5.

(2) An instantaneous step current with infinite internal resis-

tance, Figure 6.

SOURCE METAL

POLY GATE

GLASS GATE OXIDE

0

10 VOLTS

DEPLETION EDGE

40 VOLTS

n+ DRAIN

JFET

n-

MOS

n+ SOURCE

p BODY

p+

GATE

C1

C2

C6

C3

C5

C4

SOURCE

DRAIN

GATE

SOURCE

DRAIN

Application Note

October 1999

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