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MAX1292 Datasheet(PDF) 9 Page - Maxim Integrated Products |
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MAX1292 Datasheet(HTML) 9 Page - Maxim Integrated Products |
9 / 20 page 400ksps, +5V, 8-/4-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface _______________________________________________________________________________________ 9 _______________Detailed Description Converter Operation The MAX1290/MAX1292 ADCs use a successive- approximation (SAR) conversion technique and an input track-and-hold (T/H) stage to convert an analog input signal to a 12-bit digital output. Their parallel (8 + 4) out- put format provides an easy interface to standard micro- processors (µPs). Figure 2 shows the simplified internal architecture of the MAX1290/MAX1292. Single-Ended and Pseudo-Differential Operation The sampling architecture of the ADC’s analog com- parator is illustrated in the equivalent input circuits in Figures 3a and 3b. In single-ended mode, IN+ is inter- nally switched to channels CH0–CH7 for the MAX1290 (Figure 3a) and to CH0–CH3 for the MAX1292 (Figure 3b), while IN- is switched to COM (Table 3). In differen- tial mode, IN+ and IN- are selected from analog input pairs (Table 4). In differential mode, IN- and IN+ are internally switched to either of the analog inputs. This configuration is pseudo- differential in that only the signal at IN+ is sampled. The return side (IN-) must remain stable within ±0.5 LSB (±0.1 LSB for best performance) with respect to GND during a conversion. To accomplish this, connect a 0.1µF capacitor from IN- (the selected input) to GND. During the acquisition interval, the channel selected as the positive input (IN+) charges capacitor CHOLD. At the end of the acquisition interval, the T/H switch opens, retaining charge on CHOLD as a sample of the signal at IN+. The conversion interval begins with the input multiplex- er switching CHOLD from the positive input (IN+) to the negative input (IN-). This unbalances node ZERO at the comparator’s positive input. The capacitive digital-to- analog converter (DAC) adjusts during the remainder of the conversion cycle to restore node ZERO to 0V within the limits of 12-bit resolution. This action is equivalent to transferring a 12pF [(VIN+) - (VIN-)] charge from CHOLD to the binary-weighted capacitive DAC, which in turn forms a digital representation of the analog input signal. T/H THREE-STATE, BIDIRECTIONAL I/O INTERFACE 12 17k Ω 8 8 4 8 4 8 SUCCESSIVE- APPROXIMATION REGISTER MUX ( ) ARE FOR MAX1290 ONLY. CHARGE REDISTRIBUTION 12-BIT DAC CLOCK ANALOG INPUT MULTIPLEXER CONTROL LOGIC & LATCHES REF REFADJ 1.22V REFERENCE D0–D7 8-BIT DATA BUS (CH5) (CH4) CH3 CH2 CH1 CH0 COM CLK CS WR RD INT VDD HBEN GND VLOGIC MAX1290 MAX1292 AV = 2.05 COMP (CH7) (CH6) Figure 2. Simplified Functional Diagram of 8-/4-Channel MAX1290/MAX1292 |
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