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TPS73633DCQRG4 Datasheet(PDF) 11 Page - Texas Instruments |
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TPS73633DCQRG4 Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 27 page  www.ti.com APPLICATION INFORMATION Input and Output Capacitor Requirements Output Noise TPS736xx GND EN NR IN OUT V IN V OUT Optional input capacitor. May improve source impedance, noise, or PSRR. Optional output capacitor. May improve load transient, noise, or PSRR. Optional bypass capacitor to reduce output noise. V N + 32mVRMS (R 1 ) R2) R 2 + 32mVRMS V OUT V REF (1) V N(mVRMS) + 27 mVRMS V V OUT(V) (2) TPS736xx GND EN FB IN OUT V IN V OUT V OUT = × 1.204 (R 1 + R2) R 1 R 1 C FB R 2 Optional input capacitor. May improve source impedance, noise, or PSRR. Optional output capacitor. May improve load transient, noise, or PSRR. Optional capacitor reduces output noise and improves transient response. V N(mVRMS) + 8.5 mVRMS V V OUT(V) (3) TPS736xx SBVS038K – SEPTEMBER 2003 – REVISED SEPTEMBER 2005 The TPS736xx belongs to a family of new generation LDO regulators that use an NMOS pass transistor to achieve ultra-low-dropout performance, reverse cur- Although an input capacitor is not required for stab- rent blockage, and freedom from output capacitor ility, it is good analog design practice to connect a constraints. These features, combined with low noise 0.1µF to 1µF low ESR capacitor across the input and an enable input, make the TPS736xx ideal for supply near the regulator. This will counteract reac- portable applications. This regulator family offers a tive input sources and improves transient response, wide selection of fixed output voltage versions and an noise rejection, and ripple rejection. A higher-value adjustable output version. All versions have thermal capacitor may be necessary if large, fast rise-time and over-current protection, including foldback cur- load transients are anticipated or the device is lo- rent limit. cated several inches from the power source. Figure 31 shows the basic circuit connections for the The TPS736xx does not require an output capacitor fixed voltage models. Figure 32 gives the connections for stability and has maximum phase margin with no for the adjustable output version (TPS73601). R1 and capacitor. It is designed to be stable for all available R2 can be calculated for any output voltage using the types and values of capacitors. In applications where formula in Figure 32. Sample resistor values for VIN – VOUT < 0.5V and multiple low ESR capacitors common output voltages are shown in Figure 2. For are in parallel, ringing may occur when the product of best accuracy, make the parallel combination of R1 COUT and total ESR drops below 50nΩF. Total ESR and R2 approximately 19kΩ. includes all parasitic resistances, including capacitor ESR and board, socket, and solder joint resistance. In most applications, the sum of capacitor ESR and trace resistance will meet this requirement. A precision band-gap reference is used to generate the internal reference voltage, VREF. This reference is the dominant noise source within the TPS736xx and it generates approximately 32µVRMS (10Hz to 100kHz) at the reference output (NR). The regulator control loop gains up the reference noise with the same gain as the reference voltage, so that the noise voltage of the regulator is approximately given by: Figure 31. Typical Application Circuit for Fixed-Voltage Versions Since the value of VREF is 1.2V, this relationship reduces to: for the case of no CNR. An internal 27k Ω resistor in series with the noise reduction pin (NR) forms a low-pass filter for the voltage reference when an external noise reduction capacitor, CNR, is connected from NR to ground. For CNR = 10nF, the total noise in the 10Hz to 100kHz bandwidth is reduced by a factor of ~3.2, giving the approximate relationship: Figure 32. Typical Application Circuit for Adjustable-Voltage Versions for CNR = 10nF. 11 |
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