TLV5590

2BIT ANALOGTODIGITAL CONVERTER

FOR FLEXt PAGER CHIPSET

SLAS134B − NOVEMBER 1995 − REVISED NOVEMBER 1996

4

POST OFFICE BOX 655303

POST OFFICE BOX 1443

−0.5 V to 6.5 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range, EXTS0, EXTS1

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Peak input current (any input)

±20 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

−25

°C to 85°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

−65

°C to 150°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds

260

°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

MIN

NOM

MAX

UNIT

Supply voltage, AVDD, DVDD

2.7

3.3

V

Power supply ripple

0.002

Vpp

Input clock frequency, f(CLK)

38.4

kHz

Input clock duty cycle

45

50

55

%

Voltage offset applied at DC OFFSET, VI(DC OFFSET) (see Notes 1 and 2)

0.25

VDD−0.25

V

Analog input voltage, VI(pp) (See Notes 1 and 2)

VDD = 3.1 V

0.25

VDD − 0.25

Vpp

High-level control input voltage, VIH

VDD = 2.7 V to 3.3 V

0.2 DVDD

V

Low-level control input voltage, VIL

VDD = 2.7 V to 3.3 V

0.8 DVDD

V

Operating free-air temperature, TA

−25

85

°C

NOTES:

1. VI(OFFSET) =VQ − VI(DC OFFSET) where VQ is the dc quiescent voltage of the signal applied to the SIG terminal.

NOTES:

2.

V

I(PEAK) +

V

DD

2

* 0.25 V

4.217

* V

I(OFFSET)

*80 mV

The pass-band filter gain represents the maximum specified voltage gain in volts/volt of the filter. The maximum gain for the filter

is 4.217 V/V (12.5 dB). The input voltage range from this equation defines the maximum allowable input signal at the SIG terminal

with a given voltage, VI(DC OFFSET), applied at the DC OFFSET terminal and a quiescent dc input voltage, VQ, of the signal applied

at the SIG terminal. When the input voltage is within this range, the peak and valley DACs do not over range. The 80 mV value is

the tolerance on the voltage output at the MID terminal.