TLV5734

TRIPLE 8BIT 30MSPS ADC WITH HIGH

PRECISION CLAMP FOR YUV/RGB VIDEO

SLES026A − APRIL 2002 − REVISED JANUARY 2003

9

POST OFFICE BOX 655303

output data format (continued)

5 CLK

tpd

CLK

A0

A1

A2

A3

A4

A5

01

23

4

5

67

89

10

11

12

−1

−2

A6

B08

B07

C08

C07

B06

B05

C06

C05

B04

B03

C04

C03

B02

B01

C02

C01

B48

B47

C48

C47

B46

B45

C46

C45

B44

B43

C44

C43

A7

B42

B41

C42

C41

INIT

OEB B

OEB A

OEB C

OUTPUT DATA A

OUTPUT DATA B

BD[8:5]

BD[4:1] HI-Z

OUTPUT DATA C

CD8

CD7

CD[6:1] HI-Z

MSB

LSB

Figure 4. Format 1 (4:1:1) Timing Diagram

Table 5. Output Format 1 (4:1:1)

OUTPUT DATA

CHANNEL OF ADC

BIT

CLK†

CHANNEL OF ADC

BIT

6

7

8

9

10

11

12

13

A

AD8

AD7

AD6

AD5

AD4

AD3

AD2

AD1

A08

A07

A06

A05

A04

A03

A02

A01

A18

A17

A16

A15

A14

A13

A12

A11

A28

A27

A26

A25

A24

A23

A22

A21

A38

A37

A36

A35

A34

A33

A32

A31

A48

A47

A46

A45

A44

A43

A42

A41

A58

A57

A56

A55

A54

A53

A52

A51

A68

A67

A66

A65

A64

A63

A62

A61

A78

A77

A76

A75

A74

A73

A72

A71

B

BD8

BD7

BD6

BD5

BD4

BD3

BD2

BD1

B08

B07

C08

C07

Hi-Z

Hi-Z

Hi-Z

Hi-Z

B06

B05

C06

C05

Hi-Z

Hi-Z

Hi-Z

Hi-Z

B04

B03

C04

C03

Hi-Z

Hi-Z

Hi-Z

Hi-Z

B02

B01

C02

C01

Hi-Z

Hi-Z

Hi-Z

Hi-Z

B48

B47

C48

C47

Hi-Z

Hi-Z

Hi-Z

Hi-Z

B46

B45

C46

C45

Hi-Z

Hi-Z

Hi-Z

Hi-Z

B44

B43

C44

C43

Hi-Z

Hi-Z

Hi-Z

Hi-Z

B42

B41

C42

C41

Hi-Z

Hi-Z

Hi-Z

Hi-Z

C

CD8

CD7

CD6

CD5

CD4

CD3

CD2

CD1

H

L

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Hi-Z

L

L

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Hi-Z

L

L

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Hi-Z

L

H

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Hi-Z

H

L

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Hi-Z

L

L

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Hi-Z

L

L

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Hi-Z

L

H

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Hi-Z

† The first ADC sampling clock is denoted as CLK 0.

A06 is an example entry in the table where A shows the ADC channel, 0 represents the sampling order, and 6 is the bit number.