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Interface

Control

12-Bit

DAC

Holding

Latch

D(0–11)

CS

REG

WE

OUT

Power-On

Reset

x2

12

4-Bit

Control

Latch

4

Powerdown

and Speed

Control

2

Voltage

Bandgap

PGA With

Output Enable

12-Bit

DAC

Register

12

12

REF

AGND

LDAC

TLV5639C

TLV5639I

SLAS189C – MARCH 1999 – REVISED JANUARY 2004

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

FUNCTIONAL BLOCK DIAGRAM

Terminal Functions

TERMINAL

I/O/P

DESCRIPTION

NAME

NO.

AGND

14

P

Ground

CS

18

I

Chip select. Digital input active low, used to enable/disable inputs

1-10, 19,

D0-D11

I

Data input

20

LDAC

16

I

Load DAC. Digital input active low, used to load DAC output

OUT

13

O

DAC analog voltage output

REG

15

I

Register select. Digital input, used to access control register

REF

12

I/O

Analog reference voltage input/output

11

P

Positive power supply

WE

17

I

Write enable. Digital input active low, used to latch data

2