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UCC2541PWP Datasheet(PDF) 6 Page - Texas Instruments |
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UCC2541PWP Datasheet(HTML) 6 Page - Texas Instruments |
6 / 43 page UCC2541 SLUS621A − AUGUST 2004 − SEPTEMBER 2005 6 www.ti.com ELECTRICAL CHARACTERISTICS VDD = 12 V, 1-µF capacitor from VDD to GND, 1-µF capacitor from BST to SW, 1-µF capacitor from REF to GND, 0.1-µF and 2.2-µF capacitors from VDRV to PGND, CRAMP = 517 pF, RSET = 10 kΩ, TA = TJ = −40°C to 105°C, (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT G1 MAIN OUTPUT RSINK Sink resistance VSW = 0 V, VBST = 6 V, VG1 = 0.3 V 0.3 0.7 1.3 Ω RSRC Source resistance VSW = 0 V, VBST = 6 V, VG1 = 5.7 V 10 25 45 Ω ISINK Sink current(3) VSW = 0 V, VBST = 6 V, VG1 = 3.0 V 3 A ISRCE Source current(3) VSW = 0 V, VBST = 6 V, VG1 = 3.0 V −3 A tRISE Rise time CLOAD = 2.2 nF, from G1 to SW 12 25 ns tFALL Fall time CLOAD = 2.2 nF, from G1 to SW 12 25 ns G2 SYNCHRONOUS RECTIFIER OUTPUT RSINK Sink resistance VG2 = 0.3 V 5 15 30 Ω ISINK Sink current(3) VG2 = 3.25 V 3 A ISRC Source current(3) VG2 = 3.25 V −3 A tRISE Rise time CLOAD = 2.2 nF, from G2 to PGND 12 25 ns tFALL Fall time CLOAD = 2.2 nF, from G2 to PGND 12 25 ns VOH High-level output voltage, G2 VSW = GND 6.2 6.7 7.5 V DEADTIME DELAY (see Figure 1) tON(G1) RAMP rising to G1 rising 90 115 130 tOFF(G1) SYNCIN falling to G1 falling 50 70 90 tON(G2) tOFF(G2) Delay control resolution 3.5 5.0 6.5 ns tON(G2) G2 on-time minimum wrt G1 falling −24 ns tON(G2) G2 on-time maximum wrt G1 falling 62 tOFF(G2) G2 off-time minimum wrt G1 rising −68 tOFF(G2) G2 off-time maximum wrt G1 rising 10 (3) Ensured by design. Not production tested. tOFF,G1 t ON,G1 tON,G2 CLK G1 G2 tOFF,G2 G2C 2.0V V ERR RAMP Figure 1. Predictive Gate Drive Timing Diagram |
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