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TLV320AIC3120 Datasheet(PDF) 11 Page - Texas Instruments |
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TLV320AIC3120 Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 160 page  11 TLV320AIC3120 www.ti.com SLAS653B – FEBRUARY 2010 – REVISED AUGUST 2016 Submit Documentation Feedback Product Folder Links: TLV320AIC3120 Specifications Copyright © 2010–2016, Texas Instruments Incorporated (1) Maximum power dissipation is TJMAX – TA) / RθJA 5.6 Power Dissipation Ratings (1) This data was taken using 2-oz. (0,071-mm thick) trace and copper pad that is soldered to a JEDEC high-K, standard 4-layer 3-inch × 3-inch (7,62-cm × 7,62-cm) PCB. Power Rating at 25°C Derating Factor Power Rating at 70°C Power Rating at 85°C 2.3 W 28.57 mW/°C 1 W 0.6 W 5.7 I 2S, LJF, and RJF Timing in Master Mode All specifications at 25°C, DVDD = 1.8 V. Note: All timing specifications are measured at characterization but not tested at final test. See Figure 5-1. PARAMETER IOVDD = 1.1 V IOVDD = 3.3 V UNIT MIN MAX MIN MAX td(WS) WCLK delay 45 20 ns td(DO-WS) WCLK to DOUT delay (for LJF mode only) 45 20 ns td(DO-BCLK) BCLK to DOUT delay 45 20 ns ts(DI) DIN setup 8 6 ns th(DI) DIN hold 8 6 ns tr Rise time 25 10 ns tf Fall time 25 10 ns 5.8 I 2S, LJF, and RJF Timing in Slave Mode All specifications at 25°C, DVDD = 1.8 V. Note: All timing specifications are measured at characterization but not tested at final test. See Figure 5-2. PARAMETER IOVDD = 1.1 V IOVDD = 3.3 V UNIT MIN MAX MIN MAX tH(BCLK) BCLK high period 35 35 ns tL(BCLK) BCLK low period 35 35 ns ts(WS) WCLK setup 8 6 ns th(WS) WCLK hold 8 6 ns td(DO-WS) WCLK to DOUT delay (for LJF mode only) 45 20 ns td(DO-BCLK) BCLK to DOUT delay 45 20 ns ts(DI) DIN setup 8 6 ns th(DI) DIN hold 8 6 ns tr Rise time 4 4 ns tf Fall time 4 4 ns 5.9 DSP Timing in Master Mode All specifications at 25°C, DVDD = 1.8 V. Note: All timing specifications are measured at characterization but not tested at final test. See Figure 5-3. PARAMETER IOVDD = 1.1 V IOVDD = 3.3 V UNIT MIN MAX MIN MAX td(WS) WCLK delay 45 20 ns td(DO-BCLK) BCLK to DOUT delay 45 20 ns ts(DI) DIN setup 8 8 ns th(DI) DIN hold 8 8 ns tr Rise time 25 10 ns tf Fall time 25 10 ns |
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