9

UCC1857

UCC2857

UCC3857

UNITRODE CORPORATION

7 CONTINENTAL BLVD. • MERRIMACK, NH 03054

TEL. (603) 424-2410

© FAX (603) 424-3460

R

IR

I

MULT

L PK

SENSE

MULT PK

=

•

−

−

(4)

The current amplifier can be compensated using a previ-

ously presented techniques (U-134) summarized here. A

simplified high frequency model for inductor current to

duty cycle transfer function is given by

Gs

i

d

Vo

L

id

L

S

()

=

∧

∧ =

(5)

The gain of the current feedback path at the frequency of

interest (crossover) is given by

d

i

R

R

RV

L

SENSE

Z

ISE

∧

•

1

(6)

Where VSE is the ramp amplitude (p-p) which is 4.5V for

UCC3857. Combining equations. 5 and 6 yields the loop

gain of the current loop and equating it to 1 at the de-

sired crossover frequency can result in a design value for

ited to about 1/3 of the switching frequency of the con-

verter to ensure stability. See Unitrode Application Note

U-140 for further information.

Trailing Edge Delay

As shown in the waveforms of Fig. 1, the modified iso-

lated boost converter requires drive signals for the two

main (IGBT) switches and the auxiliary (MOSFET) switch

with certain timing relationships. The delay between

turn-off of an IGBT and turn-off of the MOSFET can be

programmed for the UCC1857. In a PFC application, the

input line varies from zero to the AC peak level, resulting

in a wide range of required duty ratios.

A fixed delay

time will induce line current distortion at the peaks of the

AC line under high line and/or light load conditions. This

is caused by the minimum controllable duty ratio im-

posed on the modulator by the fixed delay. If the mini-

mum controllable duty ratio is fixed, the inner current

loop can exhibit a limit cycle oscillation at the line peaks,

inducing line current distortion.

The UCC1857 has an adaptive MOSFET delay genera-

tor, which is directly modulated by load power demand.

Referring to Fig. 5, this circuit directly varies the delay

time based on the output level of the voltage error ampli-

fier, which in an average current mode PFC converter

with line feedforward is indicative of load power. The de-

nal CLK signal resets latch U2, causing PWMDEL to go

M1 and is held low until the internal PWM signal goes

low (indicating turn-off of either of the IGBT drives). At

set causing PWMDEL to go low. PWMDEL is logically

ANDed with CLK to produce the signal which commands

the MOSFET driver output (MOSDRV). The delay time,

TD1, is given by

TD

R

C

n

V

DD

VAO

1

75

75

=•

•













–

.–

.

(7)

This technique reduces the overlap delay at light loads or

high lines, but maintains a longer delay when the line

voltage is low or the load is heavy. This by definition re-

duces the minimum controllable duty ratio to an accept-

able level, and is programmable by the user. Reducing

the delay time under light current conditions is accept-

able since the IGBT current is directly proportional to

future classes of IGBT switches. The delay can also be

PWM

PWMDEL

CLK

VAO

12

DELAY

C

D

R

D

7.5V REF

CLK

MOSDRV

U2

S

R

Q

Q

Figure 5. Circuit for adaptive MOSFET delay

generation.