UCC386, UCC387, UCC388

LOW DROPOUT 200mA LINEAR REGULATOR

SLUS377B - JULY 1999 - REVISED MAY 2000

4

POST OFFICE BOX 655303

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

UCC388 Adjustable Output (continued)

Current limit duty cycle

VOUT = 0 V

12.5

14

%

Overcurrent timeout, TON

VOUT = 0 V

550

900

1250

µs

Quiescent current

OFFB = VIN

10

20

µA

Shutdown quiescent current

VIN

≤ 8.5 V,

OFFB

≤ 0.5 V

2

5

µA

Shutdown threshold (OFF)

VIN = 8.5 V

0

0.5

V

Shutdown threshold (ON)

See Note 1

VIN -

0.5 V

V

Reverse leakage current

0 V < VIN < VOUT,

VOUT < 3.35 V, at VIN

10

µA

Reverse leakage current

0 V < VIN < VOUT,

VOUT < 3.35 V, at VOUT

10

µA

Bias current at VSENSE pin

50

nA

Minimum operating voltage

2.5

V

NOTE 1: An internal 100-nA pullup is provided for this function.

pin descriptions

GND: Chip Ground. All voltages are measured with respect to this pin. This is the low-noise ground reference

for input regulation. The output decoupling capacitor should be tied between VOUT and GND.

OFFB: Shutdown, active low. This pin must be externally pulled to GND to turn off the IC. Pulling this pin high

turns on the IC. This pin is internally pulled to VIN by 100-nA current source.

VIN: Positive supply input for the regulator. Bypass this pin to GND with at least 0.1

µF of low ESR, ESL

capacitance if the source is located further than 1 inch from the device.

VOUT: Output of the regulator. The regulator does not require a minimum output capacitance for stability,

however a small capacitor is recommended to improve transient response. Choose the appropriate size

capacitor for the application with respect to the required transient loading. For example, if the load is very

dynamic, a large capacitor will smooth out the response to load steps.

VSENSE: Externally programmable voltage sense node. For the UCC388, connect resistor divider network

between VOUT, VSENSE and GND to provide custom regulation level. For the UCC386 and UCC387, connect

this pin to VOUT as close to the load as possible.

APPLICATION INFORMATION

load independent current consumption

This series of LDOs is based on CMOS circuitry and uses a high-side P-channel pass element. Consequently,

the current consumed by the LDO is extremely low at 10

µA under normal operating conditions and does not

vary with load. The shutdown mode (OFFB = GND) consumes only 2

µA, making this series an excellent choice

for battery applications.

reverse voltage standoff

These LDOs are designed to operate with the voltage at the output greater than the voltage at the input. This

can be an advantage where a circuit needs to be powered from two separate power sources that must be kept

isolated, such as selecting between one of two or more batteries.