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UCC3913DG4 Datasheet(PDF) 11 Page - Texas Instruments |
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UCC3913DG4 Datasheet(HTML) 11 Page - Texas Instruments |
11 / 21 page UCC2913 UCC3913 SLUS274A – JANUARY 1999 – REVISED APRIL 2003 11 www.ti.com APPLICATION INFORMATION Once tSTART is calculated, the power limit feature of the UCCx913 must be addressed and component values derived. Assuming the designer chooses to limit the maximum allowable average power that is associated with the circuit breaker, the power limiting resistor, RPL, can be easily determined by the following: R PL + P FET(avg) 1 mA I MAX where a minimum RPL exists defined by R PL(min) + |VSS| 10mA Finally, after computing the aforementioned variables, the minimum timing capacitor can be derived for a current source load with the following equation. C T(min) + t START 98 mA R PL ) |VSS| * 10 V 4V R PL The minimum timing capacitor can be derived for a resistive load with the following equation. C T(min) + t START 49 mA R PL ) |VSS| * 5V * IMAX R OUT ) ROUT C OUT |VSS| 2V R PL Figure 4. Possible Level Shift Circuitry Interface UDG–99003 SHUTDOWN SD/FLT 7 R4 R3 VSS LEVEL SHIFT LOCAL VDD LOCAL GND FAULT OUT UCC2913 UCC3913 0 2.5 0 75 5.0 10.0 7.5 12.5 17.5 15.0 20.0 25.0 22.5 25 50 100 175 125 150 200 Figure 5 IMAX = 4 A RPL = ∞ VFET – MOSFET Voltage– V AVERAGE POWER DISSIPATION vs MOSFET VOLTAGE RPL = 10 MΩ RPL = 5 MΩ RPL = 2 MΩ RPL = 1 MΩ RPL = 500 kΩ RPL = 200 kΩ (16) (17) (18) (19) |
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