TM8TT64JPN, TM16TT64JPN

TM8TT72JPN, TM16TT72JPN

SYNCHRONOUS DYNAMIC RAM MODULES

SMMS700A − APRIL 1998 − REVISED AUGUST 1998

10

POST OFFICE BOX 1443

electrical characteristics over recommended ranges of supply voltage and ambient temperature

TMxTTxxJPN

PARAMETER

TEST CONDITIONS

’xTTxxJPN-8

’xTTxxJPN-8A

UNIT

PARAMETER

TEST CONDITIONS

MIN

MAX

MIN

MAX

UNIT

VOH

High-level output voltage

IOH = − 2 mA

2.4

2.4

V

VOL

Low-level output voltage

IOL = 2 mA

0.4

0.4

V

II

Input current (leakage)

0 V

≤ VI ≤ VDD + 0.3 V,

All other pins = 0 V to VDD

"10

"10

µA

IO

Output current (leakage)

0 V

≤ VO ≤ VDD +0.3 V, Output disabled

"10

"10

µA

ICC1

Operating current

Burst length = 1,

tRC ≥ tRC MIN,

CAS latency = 2

115

95

mA

ICC1

Operating current

tRC ≥ tRC MIN,

IOH/IOL = 0 mA

(See Notes 4, 5, and 6)

CAS latency = 3

125

95

mA

ICC2P

Precharge standby current in

CKE

≤ VIL MAX, tCK = 15 ns (see Note 7)

1

1

mA

ICC2PS

Precharge standby current in

power-down mode

CKE and CK

≤ VIL, MAX, tCK = ∞

(see Note 8)

1

1

mA

ICC2N

Active standby current in

CKE

≥ VIH MIN, tCK = 15 ns (see Note 7)

40

40

mA

ICC2NS

Active standby current in

non-power-down mode

tCK = ∞ (see Note 8)

5

5

mA

ICC3P

Active standby current in

CKE

≤ VIL MAX, tCK = 15 ns

(see Notes 4 and 7)

8

8

mA

ICC3PS

Active standby current in

power-down mode

CKE and CK

≤ VIL MAX, tCK = ∞

(see Notes 4 and 8)

8

8

mA

ICC3N

Precharge standby current in

CKE

≥ VIH MIN,

tCK = 15 ns (see Notes 4 and 7)

50

50

mA

ICC3NS

Precharge standby current in

non-power-down mode

CKE

≥ VIH MIN,

CK

≤ VIL MAX, tCK = ∞

(see Notes 4 and 8)

15

15

mA

ICC4

Burst current

Page burst,

IOH/IOL = 0 mA

All banks activated,

CAS latency = 2

165

120

mA

ICC4

Burst current

OH OL

All banks activated,

nCCD = one cycle

(see Notes 9 and 10)

CAS latency = 3

225

165

mA

ICC5

Auto-refresh current

tRC ≤ tRC MIN

CAS latency = 2

150

150

mA

ICC5

Auto-refresh current

tRC ≤ tRC MIN

(see Notes 5 and 8)

CAS latency = 3

150

150

mA

ICC6

Self-refresh current

CKE

≤ VIL MAX

1

1

mA

† Specifications in this table represent a single SDRAM device.

NOTES:

3. All specifications apply to the device after power-up initialization. All control and address inputs must be stable and valid.

4. Only one bank is activated.

5. tRC ≥ tRCMIN

6. Control and address inputs change state twice during tRC.

7. Control and address inputs change state once every 30 ns.

8. Control and address inputs do not change state (stable).

9. Control and address inputs change once every cycle.

10. Continuous burst access, nCCD = 1 cycle