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TMDS181RGZR Datasheet(PDF) 9 Page - Texas Instruments |
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TMDS181RGZR Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 59 page  9 TMDS181, TMDS181I www.ti.com SLASE75C – AUGUST 2015 – REVISED JULY 2016 Product Folder Links: TMDS181 TMDS181I Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated (1) The typical rating is simulated at 3.3 V VCC and 1.2 V VDD and at 27°C unless otherwise noted (2) The maximum rating is simulated at 3.465 V VCC and 1.27 V VDD and at 85°C unless otherwise noted 6.6 TMDS Differential Input Electrical Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP(1) MAX(2) UNIT DR_RX_DATA_R T TMDS data lanes data rate (Retimer Mode) 0.25 6 Gbps DR_RX_DATA_R D TMDS data lanes data rate (Redriver Mode) 0.25 3.4 Gbps DR_RX_CLK TMDS clock lanes clock rate 25 340 MHz tRX_DUTY Input clock duty circle 40% 50% 60% tCLK_JIT Input clock jitter tolerance 0.3 Tbit tDATA_JIT Input data jitter tolerance Test the TTP2, see Figure 12 150 ps tRX_INTRA Input intrapair skew tolerance Test at TTP2 when DR = 1.6 Gbps, see Figure 12 112 ps tRX_INTER Input interpair skew tolerance 1.8 ns EQH(D) Fixed EQ gain for data lane IN_D(0,1,2)n/p EQ_SEL/A0 = H; fixed EQ gain, test at 6 Gbps 15 dB EQL(D) Fixed EQ gain for data lane IN_D(0,1,2)n/p EQ_SEL/A0 = L; fixed EQ gain, test at 6 Gbps 7.5 dB EQZ(D) Adaptive EQ gain for data lane IN_D(0,1,2)n/p EQ_SEL/A0 = NC; adaptive EQ (Retimer Mode Only) 2 15 dB EQ(c) EQ gain for clock lane IN_CLKn/p EQ_SEL/A0 = H,L,NC 3 dB RINT Input differential termination impedance 85 100 115 Ω VITERM Input termination voltage OE = H 3.3 3.465 V |
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