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TMP34094CPCL Datasheet(PDF) 7 Page - Texas Instruments |
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TMP34094CPCL Datasheet(HTML) 7 Page - Texas Instruments |
7 / 38 page TMS34094 ISA BUS INTERFACE SPVS006A – FEBRUARY 1992 – REVISED JUNE 1992 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 7 When a read or write access to HDATA occurs, HADDRH and HADDRL values are presented on HA5–HA31 and HCS is asserted. If a software application has properly set up the HINC, HPFW, HLB0, and HLB1 bits of HSTCTLH, and has set the AI bit of MODECTL to match HPFW in HSTCTLH, successive reads or writes to HDATA cause the TMS34020 to access sequential words in local memory. HINC HPFW AI HLB0–HLB 1 TMS34020 OPERATION TMS34094 OPERATION 0 X 0 X No autoincrement, no LAD bus half swap Increment HADDR and swap LAD bus halves after every host access† 0 X 1 X No autoincrement, no LAD bus swap Increment HADDR and swap LAD bus halves after every host write† 1 0 0 0 Autoincrement and swap LAD bus halves after every host access Increment HADDR and swap LAD bus halves after every host access 1 1 1 0 Autoincrement and swap LAD bus halves af- ter every host write Increment HADDR and swap LAD bus halves after every host write Undefined for all other combinations Undefined for all other combinations † Autoincrement host reads and writes may read or write incorrect data for these settings. To prevent host accesses from failing for these settings, the TMS34094 must force HCS to rise between accesses. In I/O mapped mode (IOE[MODECTL] = 1), write or read HADDRL and/or HADDRH to force HCS high. In memory-mapped mode (IOE[MODECTL] = 0), do not use MAP0E (set XD[MAP0E] = 1) and do not perform memory-mapped host reads if AI[MODECTL] = 1. Access to a non-sequential location requires writing the appropriate value(s) to HADDRH and HADDRL. The contents of HADDRH and HADDRL change after every host access to reflect the address of the next autoincrement access. The address stored in HADDRH and HADDRL may not properly reflect the address of the TMS34020s next host access if HINC = 0, or if HPFW, HLB0–HLB1, and AI are not set to a valid autoincrement mode shown in the table above. When the TMS34094 and TMS34020 are set up for autoincrement after writes, consecutive reads will access alternate 16-bit halves of the 32-bit data transceiver. System software should only use this mode for read-write cycles. An I/O mapped interface is generally slower than a 16-bit memory mapped interface in making random accesses to the local memory. However, it does not take up any additional host memory or I/O locations and, in a 16-bit expansion slot, it delivers better performance than an 8-bit-only memory mapped interface. When the I/O mapped interface to GSP memory is enabled, the memory mapped interface is disabled. operations I/O registers The functions of the TMS34094 are controlled through 16 registers in ISA I/O space. The registers fall into one of four categories; memory map registers (MAP0–MAP3, MAP0E, BASE0–BASE3), I/O map registers (HADDRH, HADDRL, HDATA, SHDHCTL), local memory decode registers (BKCTL, BKPORT), and a configuration register (MODECTL). MODECTL 15 14 13 12 11 10 7 6543 0 T16 SRE AI PSL IOE 16M3–16M0 HI SDD RS BE3–BE0 This register contains several of the bits which control how the TMS34094 responds to ISA bus cycles. T16, when asserted high, allows a software test to determine whether a known add-in card sharing the 128 K-bytes used by a TMS34094 memory map is a 16-bit peripheral. The mechanism suppresses the generation of M16 without enabling the byte swap logic within the TMS34094. If an 8-bit memory device shares the 128 K-byte segment, the ISA host would perform two successive 8-bit transfers on the lower half of the data bus to write a 16-bit word. Without its byte swap logic, the TMS34094 will receive both bytes with the lower half of its |
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