UCD9112_16 datasheet(4/27 Pages) TI1

Part #	UCD9112

Description	Digital Dual-Phase Synchronous Buck Controller

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Manufacturer	TI1 [Texas Instruments]

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t

(HD:STA)

t

(HD:DAT)

t

(SU:DAT)

t

(SU:STA)

t

(SU:STO)

t

(HD:STA)

t

(HIGH)

t

(LOW)

t

(BUF)

t

r

t

f

SCLK

SDATA

NOTE:(1)SCLK

istheacknowledge-relatedclockpulsegeneratedbythemaster.

ACK

SCLK

Start

Stop

P

S

P

t

(LOW:SEXT)

t

(LOW:MEXT)

t

(LOW:MEXT)

t

(LOW:MEXT)

SCLK

ACK

(1)

SCLK

ACK

(1)

Not Recommended for New Designs

UCD9112

SLVS711A – SEPTEMBER 2006 – REVISED JUNE 2007

www.ti.com

ELECTRICAL CHARACTERISTICS (continued)

VD33 = 3.3V, TA = –40°C to 125°C (unless otherwise noted).

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

PMBus/SMBus

FSMB PMBus/SMBus operating frequency

Slave mode, SMBC 50% duty cycle

100

kHz

Bus free time between start and stop t(BUF)

4.7

ms

Hold time after (repeated) start

t(HD:STA)

4.0

ms

Repeated start setup time

t(SU:STA)

4.7

ms

Stop setup time

t(SU:STO)

4.0

ms

Receive Mode

0

ns

Data hold time

t(HD:DAT)

Transmit Mode

300

ns

Data setup time

t(SU:DAT)

250

ns

Error signal/detect(1)

t(TIMEOUT)

25

35

ms

Clock low period

t(LOW)

4.7

ms

Clock high period(2)

t(HIGH)

4.0

50

ms

Cumulative clock low slave extend

t(LOW:SEXT)

25

ms

time(3)

Cumulative clock low master extend

t(LOW:MEXT)

10

ms

time(4)

Clock/data fall time(5)

tf

300

ns

Clock/data rise time(6)

tr

1000

ns

(1)

The UCD9112 times out when any clock low exceeds t(TIMEOUT).

(2)

t(HIGH), Max, is the minimum bus idle time. SMBC = SMBD = 1 for t > 50 ms causes reset of any transaction involving UCD9112 that is

in progress. This specification is valid when the NC_SMB control bit remains in the default cleared state (CLK[0]=0).

(3)

t(LOW:SEXT) is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop.

(4)

t(LOW:MEXT) is the cumulative time a master device is allowed to extend the clock cycles in one message from initial start to the stop.

(5)

Fall time tf = 0.9VDD to (VILMAX – 0.15)

(6)

Rise time tr = ( VILMAX – 0.15) to (VIHMIN + 0.15)

Figure 1. PMBus/SMBus Timing Diagram

4

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