6

COMMERCIALANDINDUSTRIALTEMPERATURERANGES

IDT23S09

3.3VZERODELAYCLOCKBUFFER

Output

1.4V

1.4V

t5

Output

REF

t6

Output

CLKOUT

Device 1

t7

CLKOUT

Device 2

1.4V

1.4V

t2

t1

1.4V

2V

0.8V

t3

t4

0.8V

3.3V

0V

2V

Output

ZERO DELAY AND SKEW CONTROL

All outputs should be uniformly loaded in order to achieve Zero I/O Delay. Since the CLKOUT pin is the internal feedback for the PLL, its relative

loading can affect and adjust the input/output delay. The Output Load Difference diagram illustrates the PLL's relative loading with respect to the other

outputs that can adjust the Input-Output (I/O) Delay.

For designs utilizing zero I/O Delay, all outputs including CLKOUT must be equally loaded. Even if the output is not used, it must have a capacitive

load equal to that on the other outputs in order to obtain true zero I/O Delay. For zero output-to-output skew, all outputs must be loaded equally.

All Outputs Rise/Fall Time

Input to Output Propagation Delay

Device to Device Skew

Output to Output Skew

Duty Cycle Timing

SWITCHING WAVEFORMS