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TMS320C6748EZWTD4 Datasheet(PDF) 2 Page - Texas Instruments |
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TMS320C6748EZWTD4 Datasheet(HTML) 2 Page - Texas Instruments |
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2 / 273 page  TMS320C6748 SPRS590F – JUNE 2009 – REVISED MARCH 2014 www.ti.com • One Host-Port Interface (HPI) with 16-Bit-Wide • Universal Parallel Port (uPP): Muxed Address and Data Bus For High Bandwidth – High-Speed Parallel Interface to FPGAs and • Programmable Real-Time Unit Subsystem Data Converters (PRUSS) – Data Width on Both Channels is 8- to 16-Bit – Two Independent Programmable Real-Time Unit Inclusive (PRU) Cores – Single-Data Rate or Dual-Data Rate Transfers • 32-Bit Load-Store RISC Architecture – Supports Multiple Interfaces with START, ENABLE, and WAIT Controls • 4KB of Instruction RAM Per Core • Serial ATA (SATA) Controller: • 512 Bytes of Data RAM Per Core – Supports SATA I (1.5 Gbps) and SATA II • PRUSS can be Disabled via Software to (3.0 Gbps) Save Power – Supports All SATA Power-Management • Register 30 of Each PRU is Exported From Features the Subsystem in Addition to the Normal R31 Output of the PRU Cores. – Hardware-Assisted Native Command Queueing (NCQ) for up to 32 Entries – Standard Power-Management Mechanism – Supports Port Multiplier and Command-Based • Clock Gating Switching • Entire Subsystem Under a Single PSC Clock • Real-Time Clock (RTC) with 32-kHz Oscillator and Gating Domain Separate Power Rail – Dedicated Interrupt Controller • Three 64-Bit General-Purpose Timers (Each – Dedicated Switched Central Resource Configurable as Two 32-Bit Timers) • USB 1.1 OHCI (Host) with Integrated PHY (USB1) • One 64-Bit General-Purpose or Watchdog Timer • USB 2.0 OTG Port with Integrated PHY (USB0) (Configurable as Two 32-Bit General-Purpose – USB 2.0 High- and Full-Speed Client Timers) – USB 2.0 High-, Full-, and Low-Speed Host • Two Enhanced High-Resolution Pulse Width – End Point 0 (Control) Modulators (eHRPWMs): – End Points 1,2,3,4 (Control, Bulk, Interrupt, or – Dedicated 16-Bit Time-Base Counter with ISOC) RX and TX Period and Frequency Control • One Multichannel Audio Serial Port (McASP): – 6 Single-Edge Outputs, 6 Dual-Edge Symmetric – Two Clock Zones and 16 Serial Data Pins Outputs, or 3 Dual-Edge Asymmetric Outputs – Supports TDM, I2S, and Similar Formats – Dead-Band Generation – DIT-Capable – PWM Chopping by High-Frequency Carrier – FIFO Buffers for Transmit and Receive – Trip Zone Input • Two Multichannel Buffered Serial Ports (McBSPs): • Three 32-Bit Enhanced Capture (eCAP) Modules: – Supports TDM, I2S, and Similar Formats – Configurable as 3 Capture Inputs or 3 Auxiliary – AC97 Audio Codec Interface Pulse Width Modulator (APWM) Outputs – Telecom Interfaces (ST-Bus, H100) – Single-Shot Capture of up to Four Event Time- Stamps – 128-Channel TDM • Packages: – FIFO Buffers for Transmit and Receive – 361-Ball Pb-Free Plastic Ball Grid Array (PBGA) • 10/100 Mbps Ethernet MAC (EMAC): [ZCE Suffix], 0.65-mm Ball Pitch – IEEE 802.3 Compliant – 361-Ball Pb-Free PBGA [ZWT Suffix], – MII Media-Independent Interface 0.80-mm Ball Pitch – RMII Reduced Media-Independent Interface • Commercial, Extended, or Industrial Temperature – Management Data I/O (MDIO) Module • Video Port Interface (VPIF): – Two 8-Bit SD (BT.656), Single 16-Bit or Single Raw (8-, 10-, and 12-Bit) Video Capture Channels – Two 8-Bit SD (BT.656), Single 16-Bit Video Display Channels 2 TMS320C6748 Fixed- and Floating-Point DSP Copyright © 2009–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320C6748 |
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