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TMS320DM6467TZUTD1 Datasheet(PDF) 9 Page - Texas Instruments |
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TMS320DM6467TZUTD1 Datasheet(HTML) 9 Page - Texas Instruments |
9 / 352 page TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 Table 3-1. Characteristics of the DM6467T Processor (continued) HARDWARE FEATURES DM6467T Size (Bytes) 248KB RAM, 8KB ROM DSP • 32KB L1 Program (L1P)/Cache (up to 32KB) • 32KB L1 Data (L1D)/Cache (up to 32KB) • 128KB Unified Mapped RAM/Cache (L2) On-Chip Memory Organization ARM • 16KB I-cache • 8KB D-cache • 32KB RAM • 8KB ROM CPU ID + CPU Rev ID Control Status Register (CSR.[31:16]) 0x1000 C64x+ Megamodule Revision ID Register (MM_REVID[15:0]) 0x0000 Revision (address location: 0x0181 2000) JTAGID Register See Section 7.29.1, JTAG ID (JTAGID) Register JTAG BSDL_ID (address location: 0x01C4 0028) Description(s) DSP 1 GHz (-1G) CPU Frequency MHz ARM926 500 MHz(-1G) DSP 1.0 ns (-1G) Cycle Time ns ARM926 2.0 ns (-1G) Voltage Core (V) 1.3 V (-1G) I/O (V) 1.8 V, 3.3 V (-1G) DEV_CLKIN frequency multiplier (PLLC1) x1 (Bypass), x14 to x32 (-1G) (Between 27 – 35-MHz range) PLL Options DEV_CLKIN frequency multiplier (PLLC2) x1 (Bypass), x14 to x32 (-1G) (Between 27 – 35-MHz range) AUX_CLKIN frequency 24/48-MHz reference BGA Package 19 x 19 mm 529-Pin BGA (CUT) Process Technology μm 0.09 μm Product Preview (PP), Product Status(2) Advance Information (AI), PD or Production Data (PD) (2) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009–2012, Texas Instruments Incorporated Device Overview 9 Submit Documentation Feedback Product Folder Link(s): TMS320DM6467T |
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