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TMX320DM8148BCYE Datasheet(PDF) 8 Page - Texas Instruments |
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TMX320DM8148BCYE Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 376 page  TMS320DM8148, TMS320DM8147 SPRS647E – MARCH 2011 – REVISED DECEMBER 2013 www.ti.com Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. This data manual revision history highlights the technical changes made to the SPRS647D device-specific data manual to make it an SPRS647E revision. Scope: Applicable updates to the DM814x DaVinci™ Video DMP device family, specifically relating to the TMS320DM8148/47 devices (Silicon Revisions 3.0, 2.1), which are now in the production data (PD) stage of development have been incorporated. • Updated/Changed Power-Up Sequence • Updated/Changed Power-Down Sequence • Low-end OPP combinations no longer supported (CVDD_x < CVDD) • Added RXACTIVE Function (Bit 18) to PINCTRLx Register Description • Added Power-On Hours (POH) section • Added Latch-Up Performance Absolute Maximum Ratings • DDR2/DDR3 supports up to 533 MHz • OPP50 is not supported • SmartReflex™ (AVS) is not supported • Deep Sleep Mode is not supported • HDMI HDCP encryption is not supported SEE ADDITIONS/MODIFICATIONS/DELETIONS • Replaced all instances of "DSP/EDMA MMU" with "System MMU" • Deleted all references to OPP50 and Deep Sleep Mode Global • Deleted the TMS320DM8146 device along with any device-specific information; no longer supported • Updated/Changed description the HD Video Processing Subsystem (HDVPSS) Section 1 • Updated/Changed the Dual 32-Bit DDR2/DDR3 SDRAM Interfaces sub-bullet from "Supports up to Features DDR2-800 and DDR3-800" to "Supports up to DDR2-800 and DDR3-1066" Table 2-2, Characteristics of the Processor: Section 2.2 • Updated/Changed the HD Video Processing Subsystem (HDVPSS) row Device Characteristics • Updated/Changed Core Logic (V), OPP100, OPP120 range from "0.95 V – 1.20 V" to "1.10 V – 1.20 V" Table 2-7, L4 Slow Peripheral Memory Map: Section 2.12.4.2 • Updated/Changed 0x4818_8000–0x4818_BFFF Device Name from "SmartReflex0/1 Peripheral L4 Slow Peripheral and Support Registers" to "Reserved" Memory Map • Updated/Changed 0x4819_0000–0x4819_3FFF Device Name from "SmartReflex2/3 Peripheral and Support Registers" to "Reserved" Table 3-11, GP1 Terminal Functions: Section 3.2.7 General-Purpose • Added "The ENLVCMOS bit in the MLBP_DAT_IO_CTRL register...." to the pin descriptions for Input/Outputs (GPIOs) pins GP1[10:7] (V2, V1, W2, and W1 respectively). Table 3-48, Reserved Terminal Functions: Section 3.2.25 Reserved Pins • Updated/Changed TYPE for Signal No. Y14 (RSV4) and AC8 (RSV5) from "S" to "I" 8 Contents Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320DM8148 TMS320DM8147 |
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