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TMS320F28031 Datasheet(PDF) 5 Page - Texas Instruments |
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TMS320F28031 Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 160 page  5 TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 www.ti.com SPRS584K – APRIL 2009 – REVISED JUNE 2016 Submit Documentation Feedback Product Folder Links: TMS320F28030 TMS320F28031 TMS320F28032 TMS320F28033 TMS320F28034 TMS320F28035 Revision History Copyright © 2009–2016, Texas Instruments Incorporated 2 Revision History Changes from October 7, 2013 to June 24, 2016 (from J Revision (October 2013) to K Revision) Page • Global: Changed product status of TMS320F2803x 56-pin RSH devices from TMX (experimental device) to TMS (fully qualified production device). ........................................................................................... 1 • Global: Restructured document. .................................................................................................. 1 • Global: Added ESD Ratings table; Detailed Description section; Device and Documentation Support section; and Mechanical Packaging and Orderable Information section. ............................................................... 1 • Global: Removed "Analog MUX" table (this was Table 4-21 in SPRS584J). ............................................... 1 • Global: Removed references to the Reliability Data for TMS320LF24xx and TMS320F28xx Devices Application Report. ................................................................................................................................. 1 • Global: Replaced "CAN 2.0B" with "ISO11898-1 (CAN 2.0B)". ............................................................... 1 • Section 1.1 (Features): Removed "Dynamic PLL Ratio Changes Supported" feature. ..................................... 1 • Device Information: Added table. .................................................................................................. 2 • Table 3-1 (Device Comparison): Changed title from "Hardware Features" to "Device Comparison". .................... 6 • Table 3-1: Removed "Product status" row and associated footnote. ......................................................... 6 • Section 3.1 (Related Products): Added section. ................................................................................. 8 • Section 4.2 (Signal Descriptions): Updated NOTE. ............................................................................ 13 • Table 4-1 (Signal Descriptions): Changed title from "Terminal Functions" to "Signal Descriptions". .................... 13 • Table 4-1: Updated DESCRIPTION of X1, XRS, VREFHI, VREFLO, VDD, and VDDIO. ......................................... 13 • Section 5.1 (Absolute Maximum Ratings): Added Input voltage, VIN (X1). ................................................. 21 • Section 5.3 (Recommended Operating Conditions): Changed "Junction temperature, TJ" to "Ambient temperature, TA" for T version and S version. .................................................................................. 22 • Section 5.3: Removed "VDDIO and VDDA should be maintained within ~0.3 V of each other" footnote. .................. 22 • Section 5.4 (Power Consumption Summary): Changed section title from "Current Consumption" to "Power Consumption Summary". .......................................................................................................... 23 • Section 5.11 (Power Sequencing): Updated "There is no power sequencing requirement needed ..." paragraph. ... 32 • Table 5-7 (Internal Zero-Pin Oscillator (INTOSC1/INTOSC2) Characteristics): Updated footnote about oscillator accuracy. ............................................................................................................................ 36 • Figure 6-5 (VREG + POR + BOR + Reset Signal Connectivity): Updated figure. ......................................... 60 • Table 6-13 (PLL, Clocking, Watchdog, and Low-Power Mode Registers): Added PCLKCR2. .......................... 61 • Figure 6-6 (Clock and Reset Domains): Added PCLKCR2. .................................................................. 62 • Section 6.6.2 (Crystal Oscillator Option): Added "The on-chip crystal oscillator X1 and X2 pins are 1.8-V level signals ..." paragraph. .............................................................................................................. 64 • Figure 6-11 (CPU-watchdog Module): Updated figure. ........................................................................ 68 • Table 6-37 (SPI Master Mode External Timing (Clock Phase = 0)): Parameter 9 [tv(SPCL-SOMI)M, tv(SPCH-SOMI)M]: Changed MIN values to 0. ......................................................................................................... 97 • Table 6-38 (SPI Master Mode External Timing (Clock Phase = 1)): Parameter 11 [tv(SPCH-SOMI)M, tv(SPCL-SOMI)M]: Changed MIN values to 0. ......................................................................................................... 99 • Table 6-39 (SPI Slave Mode External Timing (Clock Phase = 0)): Parameter 16 [tv(SPCL-SOMI)S, tv(SPCH-SOMI)S]: Changed MIN values to 0. ....................................................................................................... 101 • Table 6-40 (SPI Slave Mode External Timing (Clock Phase = 1)): Parameter 18 [tv(SPCL-SOMI)S, tv(SPCH-SOMI)S]: Changed MIN values to 0. ....................................................................................................... 102 • Section 6.9.15 (Pin Multiplexing): Changed title from "GPIO MUX" to "General-Purpose Input/Output (GPIO) MUX". ............................................................................................................................... 132 • Table 6-64 (Analog MUX for 80-Pin PN Package): Added table. .......................................................... 134 • Table 6-65 (Analog MUX for 56-Pin RSH and 64-Pin PAG Packages): Added table. ................................... 135 • Section 7 (Applications, Implementation, and Layout): Added section. .................................................... 144 • Section 8 (Device and Documentation Support): Added section. .......................................................... 145 • Section 8.1 (Getting Started): Updated links. ................................................................................. 145 • Section 8.3 (Tools and Software): Added section. ........................................................................... 146 • Section 8.4 (Documentation Support): Updated section. .................................................................... 147 • Section 9.1 (Packaging Information): Updated section. ...................................................................... 150 |
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