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TMS320C242PGA Datasheet(PDF) 3 Page - Texas Instruments |
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TMS320C242PGA Datasheet(HTML) 3 Page - Texas Instruments |
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3 / 74 page  TMS320C242 DSPCONTROLLER SPRS063D − DECEMBER 1997 − REVISED SEPTEMBER 2000 3 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 REVISION HISTORY REVISION DATE PRODUCT STATUS HIGHLIGHTS D September 2000 Production Data The internal pullup/pulldown information has been corrected for the pins as appropriate. This information can be found in the “Terminal Functions” section of the data sheet. Errors in the memory map have been rectified with respect to re- served and illegal addresses. SPI and CAN register spaces have been marked as “Illegal”. Changes have been made to improve the clarity of the memory maps. The functional diagram depicting the operation of the GPIO pins has been modified to enhance the understanding of pin behavior. The bit positions for the PIRQRn and PIACKRn registers have been corrected in Table 5 to reflect the silicon. The input currents (II) have been specified separately for pins with pullup and pulldown. The IDD specification now includes a “Typical” number. The LPM2 current number has been changed from 75 µA to 5 mA. The figure corresponding to “IDLE2 Entry and Exit Timing” for LPM1 mode has been removed. Note that the parameters are identical to LPM0. The “Reset Timing” figure now includes the state of the GPIO pins for “Power-on” reset. Table 14, “Differences Between the TMS320F241 and the TMS320C242 Devices”, has been added to aid migration from Flash to ROM designs. |
Similar Part No. - TMS320C242PGA |
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Similar Description - TMS320C242PGA |
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