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TMS320C242 Datasheet(PDF) 8 Page - Texas Instruments |
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TMS320C242 Datasheet(HTML) 8 Page - Texas Instruments |
8 / 74 page TMS320C242 DSPCONTROLLER SPRS063D − DECEMBER 1997 − REVISED SEPTEMBER 2000 8 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Terminal Functions - C242 PG and FN Packages (Continued) NAME 64-PIN QFP 68-PIN PLCC TYPE† RESET STATE‡ DESCRIPTION NAME NO. NO. TYPE† STATE‡ DESCRIPTION EVENT MANAGER (CONTINUED) PDPINT 58 1 I I Power drive protection interrupt input. This interrupt, when activated, puts the PWM output pins in the high-impedance state, should motor drive/power converter abnormalities, such as overvoltage or overcurrent, etc., arise. PDPINT is a falling-edge-sensitive interrupt. After the falling edge, this pin must be held low for two clock cycles for the core to recognize the interrupt. BIT I/O PINS IOPC2 § 45 56 I/O GPIO ( ↓) IOPC3 § 46 57 I/O GPIO ( ↓) IOPC4 § 47 58 I/O I GPIO ( ↓) IOPC5 § 48 59 I/O I GPIO ( ↓) IOPC6 § 4 11 I/O GPIO ( ↓) IOPC7 § 3 10 I/O GPIO ( ↓) SERIAL COMMUNICATIONS INTERFACE (SCI) AND BIT I/O PINS SCITXD/IOPA0 43 54 I/O I SCI asynchronous serial port transmit data or GPIO SCIRXD/IOPA1 44 55 I/O I SCI asynchronous serial port receive data or GPIO INTERRUPT, EXTERNAL ACCESS, AND MISCELLANEOUS SIGNALS RS 27 35 I/O I Device reset. RS causes the C242 to terminate execution and sets PC=0. After RS is brought to a high level, execution begins at location zero of program memory. RS affects (sets to zero) various registers and status bits. When the watchdog timer overflows, it initiates a system reset pulse that is reflected on the RS pin. This pulse is eight clock cycles wide. NMI¶ 53 64 I I Nonmaskable interrupt. When NMI is activated, the device is interrupted regardless of the state of the INTM bit of the status register. NMI is (falling) edge- and low-level-sensitive. To be recognized by the core, this pin must be kept low for at least one clock cycle after the falling edge. ( ↑) XINT1/IOPA2 § 55 66 I/O I External user interrupt 1 or GPIO. Both XINT1 and XINT2 are edge- sensitive. To be recognized by the core, these pins must be kept low/high for at least one clock cycle after the edge. The edge polarity is programmable. ( ↓) XINT2/ADCSOC/IOPD1 54 65 I/O I External user interrupt 2. External “start-of-conversion” input for ADC/GPIO. Both XINT1 and XINT2 are edge-sensitive. To be recognized by the core, these pins must be kept low/high for at least one clock cycle after the edge. The edge polarity is programmable. † I = input, O = output, Z = high impedance ‡ The reset state indicates the state of the pin at reset. If the pin is an input, indicated by an I, its state is determined by user design. If the pin is an output, its level at reset is indicated. § These pins are internally pulled low. However, these pins are not internally pulled low in F243/F241. ¶ These pins are internally pulled high. However, these pins are not internally pulled high in F243/F241. # The PMT pin should be connected to GND on F243/F241. On the C242, this pin can be left open or connected to GND. NOTE: Bold, italicized pin names indicate pin function after reset. LEGEND: ↑ − Internal pullup ↓ − Internal pulldown (Typical active pullup/pulldown value is 150 µA.) |
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