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TMDS3200051 Datasheet(PDF) 5 Page - Texas Instruments |
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TMDS3200051 Datasheet(HTML) 5 Page - Texas Instruments |
5 / 44 page TMS320C511A DIGITAL SIGNAL PROCESSOR SPRS053 – FEBRUARY 1997 5 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 Pin Functions for a TMS320C511A Device in the PJ/PZ Package (Continued) SIGNAL TYPE DESCRIPTION EMULATION/IEEE 1149.1 (JTAG) INTERFACE TDI I IEEE 1149.1 test-access-port scan data input TDO O/Z IEEE 1149.1 test-access-port scan data output TMS I IEEE 1149.1 test-access-port mode-select input TCK I IEEE 1149.1 test-access-port clock input TRST I IEEE 1149.1 test-access-port reset (with pulldown resistor). TRST disables JTAG when low. EMU0 I/O/Z Emulation control 0. EMU0 is reserved for emulation use. EMU1/OFF I/O/Z Emulation control 1. EMU1/OFF puts outputs in the high-impedance state when low. CLOCK GENERATION AND CONTROL X1 O Divide-by-two oscillator output X2/CLKIN I Divide-by-two clock/oscillator input CLKMD1, CLKMD2, CLKMD3 I Clock-mode select inputs CLKOUT1 O/Z Device system-clock output POWER SUPPLY CONNECTIONS VDDA S Supply connection, address-bus output VDDD S Supply connection, data-bus output VDDC S Supply connection, control output VDDI S Supply connection, internal logic VSSA S Supply connection, address-bus output VSSD S Supply connection, data-bus output VSSC S Supply connection, control output VSSI S Supply connection, internal logic Legend: I = Input O = Output Z = High impedance S = Supply architecture The ’C511A’s advanced Harvard-type architecture maximizes processing power by maintaining two memory bus structures — program and data — for full-speed execution. Instructions support data transfers between the two spaces. This architecture permits coefficients that are stored in program memory to be read into the RAM, thereby eliminating the need for a separate coefficient ROM. It also makes available immediate instructions and subroutines based on computed values. Increased throughput on the ’C511A for many DSP applications is accomplished by means of single-cycle multiply/accumulate instructions with a data-move option, up to eight auxiliary registers with a dedicated arithmetic unit, and faster I/O necessary for data-intensive signal processing. The architecture emphasizes overall speed, communication, and flexibility in processor configuration. Control signals and instructions provide floating-point support, block-memory transfers, communication to slower off-chip devices, and multiprocessing implementations (see the functional block diagram). Table 2 explains the symbols that are used in the functional block diagram. |
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