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TMS320C6201GJLA200 Datasheet(PDF) 2 Page - Texas Instruments |
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TMS320C6201GJLA200 Datasheet(HTML) 2 Page - Texas Instruments |
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2 / 70 page  TMS320C6201 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004 2 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 Table of Contents parameter measurement information 30 ............... input and output clocks 31 ........................... asynchronous memory timing 33 ..................... synchronous-burst memory timing 35 ................. synchronous DRAM timing 39 ....................... HOLD/HOLDA timing 43 ............................ reset timing 44 ..................................... external interrupt timing 46 .......................... host-port interface timing 47 ......................... multichannel buffered serial port timing 50 ............. DMAC, timer, power-down timing 61 .................. JTAG test-port timing 62 ............................ revision history 63 .................................. thermal/mechanical data 64 ......................... GJC/GJL BGA packages (bottom view) 1 ................. description 2 ......................................... device characteristics 3 ................................ functional and CPU (DSP core) block diagram 4 ........... CPU (DSP core) description 5 .......................... signal groups description 7 ............................. signal descriptions 9 ................................... development support 20 ............................... documentation support 23 .............................. clock PLL 24 ......................................... power-down mode logic 25 ............................. power-supply sequencing 27 ........................... absolute maximum ratings over operating case temperature ranges 28 ............................ recommended operating conditions 28 ................... electrical characteristics over recommended ranges of supply voltage and operating case temperature 29 .... description The TMS320C62x™ DSPs (including the TMS320C6201†) are the fixed-point DSP family in the TMS320C6000™ DSP platform. The C6201 device is based on the high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for multichannel and multifunction applications. With performance of up to 1600 MIPS at a clock rate of 200 MHz, the C6201 offers cost-effective solutions to high-performance DSP programming challenges. The C6201 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight functional units provide six arithmetic logic units (ALUs) for a high degree of parallelism and two 16-bit multipliers for a 32-bit result. The C6201 can produce two multiply-accumulates (MACs) per cycle—for a total of 466 million MACs per second (MMACS). The C62x™ DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The C6201 includes a large bank of on-chip memory and has a powerful and diverse set of peripherals. Program memory consists of a 64K-byte block that is user-configurable as cache or memory-mapped program space. Data memory of the C6201 consists of two 32K-byte blocks of RAM for improved concurrency. The peripheral set includes two multichannel buffered serial ports (McBSPs), two general-purpose timers, a host-port interface (HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM or SBSRAM and asynchronous peripherals. The C62x™ DSP has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution. TMS320C6000 and C62x are trademarks of Texas Instruments. Windows is a registered trademark of the Microsoft Corporation. † The TMS320C6201 device shall be referred to as C6201 throughout the remainder of this document. |
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