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TMS29F040 Datasheet(PDF) 8 Page - Texas Instruments |
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TMS29F040 Datasheet(HTML) 8 Page - Texas Instruments |
8 / 37 page TMS29F040 524288 BY 8BIT FLASH MEMORY SMJS820C − APRIL 1996 − REVISED JUNE 1998 8 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 byte-program command (continued) the fourth bus cycle, and then the rising edge of W starts the byte-program operation. The embedded byte-programming function automatically provides needed voltage and timing to program and to verify the cell margin. Any further commands written to the device during the program operation are ignored. Programming can be performed at any address location in any order, resulting in logic 0s being programmed into the device. Attempting to program logic 1 into a bit that has been previously programmed to a logic 0 causes the internal pulse counter to exceed the pulse-count limit. This sets the exceed-timing-limit indicator (DQ5) to a logic-high state. Only an erase operation can change bits from logic 0s to logic 1s. When erased, all bits are in a logic 1 state. Figure 3 shows a flow chart of the typical byte-programming operation. The status of the device during the automatic programming operation can be monitored for completion using the data-polling feature or the toggle-bit feature. See the operation status section for a full description. chip-erase command Chip erase is a six-bus-cycle command sequence. The first three bus cycles put the device into the erase-setup state. The next two bus cycles unlock the erase mode, and then the sixth bus cycle loads the chip-erase command. This command sequence is required to ensure that the memory contents are not erased accidentally. The rising edge of W starts the chip-erase operation. Any further commands written to the device during the chip-erase operation are ignored. The embedded chip-erase function automatically provides the voltage and timing needed to program and verify all the memory cells prior to electrical erase, and then erases and verifies the cell margin automatically. The user is not required to program the memory cells prior to erase. The status of the device during the automatic chip-erase operation can be monitored for completion using the data-polling feature or the toggle-bit feature. See the operation status section for a full description. Figure 6 shows a flow chart of the typical chip-erase operation. sector-erase command Sector erase is a six-bus-cycle command sequence. The first three bus cycles cause the device to go into the erase-setup state. The next two bus cycles unlock the erase mode, and the sixth bus cycle loads the sector-erase command and the sector-address location to be erased. Any address location within the desired sector can be used. The addresses are latched on the falling edge of W and the sector-erase command (30h) is latched on the rising edge of W in the sixth bus cycle. After a delay of 80 µs from the rising edge of W, the sector-erase operation begins on the selected sector(s). Additional sectors can be selected to be erased concurrently during the sector-erase command sequence. For each additional sector selected for erase, another bus cycle is issued. The bus cycle loads the next sector-address location and the sector-erase command. The time between the end of the previous bus cycle and the start of the next bus cycle must be less than 80 µs—otherwise, the new sector location is not loaded. A time delay of 80 µs from the rising edge of the last W starts the sector-erase operation. If there is a falling edge of W within the 80- µs time delay, the timer is reset. One to eight sector-address locations can be loaded in any order. The state of the delay timer can be monitored using the sector-erase-delay indicator (DQ3). If DQ3 is logic low, the time delay has not expired. See the operation status section for a description. Any command other than erase-suspend (B0h) or sector-erase (30h) written to the device during the sector-erase operation causes the device to exit the sector-erase mode and the contents of the sector(s) selected for erase are no longer valid. To complete the sector-erase operation, the sector-erase command sequence must be repeated. The embedded sector-erase function automatically provides needed voltage and timing to program and to verify all of the memory cells prior to electrical erase and then erases and verifies the cell margin automatically. Programming the memory cells prior to erase is not required. The status of the device during the automatic |
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