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TMS29F040 Datasheet(PDF) 10 Page - Texas Instruments |
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TMS29F040 Datasheet(HTML) 10 Page - Texas Instruments |
10 / 37 page TMS29F040 524288 BY 8BIT FLASH MEMORY SMJS820C − APRIL 1996 − REVISED JUNE 1998 10 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 data-polling (DQ7) The data-polling status function outputs the complement of the data latched into the DQ7 data register while the write-state machine is engaged in a program or erase operation. Data bit DQ7 changes from complement to true to indicate the end of an operation. Data-polling is available only during the byte-programming, chip-erase, sector-erase, and sector-erase timing delay. Data-polling is valid after the rising edge of W in the last bus cycle of the command sequence loaded into the command register. Figure 10 shows a flow chart of the data-polling operation. During a byte-program operation, reading DQ7 outputs the complement of the DQ7 data to be programmed at the selected address location. Upon completion, reading DQ7 outputs the true DQ7 data loaded into the program data register. During erase operations, reading DQ7 outputs a logic 0. Upon completion, reading DQ7 outputs a logic 1. Also, data-polling must be performed at a sector address that is within a sector being erased; otherwise, the status is not valid. When using data-polling, the address must remain stable throughout the operation. During a data-polling read, while G is low, DQ7 can change asynchronously with the other DQ’s. Depending on the read timing, the system can read valid data on DQ7, while other DQ pins are still invalid. The data on DQ0−DQ7 is valid with a subsequent read of the device. Figure 11 shows the data-polling timing diagram. toggle bit (DQ6) The toggle-bit status function outputs data on DQ6 that toggles between logic 1 and logic 0 while the write-state machine is engaged in a program or erase operation. When toggle bit DQ6 stops toggling after two consecutive reads to the same address, the operation is complete. The toggle bit is only available during the byte-programming, chip-erase, sector-erase, and sector-erase timing delay. Toggle-bit data is valid after the rising edge of W in the last bus cycle of the command sequence loaded into the command register. Figure 12 shows a flow chart of the toggle-bit status-read algorithm. Depending on the read timing, DQ6 can stop toggling while other DQ pins are still invalid. The data on DQ0−DQ7 is valid with a subsequent read of the device. Figure 13 shows the toggle-bit timing diagram. exceed-time-limit bit (DQ5) The program and erase operations use an internal pulse counter to limit the number of pulses applied. If the pulse count limit is exceeded, DQ5 is set to a logic 1, indicating that the program or erase operation has failed. DQ7 does not change from complemented data to true data and DQ6 does not stop toggling when read. To continue operation, the device must be reset. This condition occurs when attempting to program a logic 1 into a bit that has been programmed previously to a logic 0. Only an erase operation can change bits from logic 0 to logic 1. After reset, the device is functional and can be erased and reprogrammed. sector-load-timer bit (DQ3) The sector-load-timer status bit, DQ3, is used to determine if the time to load additional sector addresses has expired. After completion of a sector-erase command sequence, DQ3 remains at a logic low for 80 µs. This indicates that another sector-erase command sequence can be issued. If DQ3 is at a logic high, it indicates that the delay has expired and attempts to issue additional sector-erase commands are ignored. See the sector-erase command section for a description. The data-polling bit and toggle bit are valid during the 80- µs time delay and can be used to determine if a valid sector-erase command has been issued. To ensure additional sector-erase commands have been accepted, the status of DQ3 should be read before and after each additional sector-erase command. If DQ3 is at a logic low on both reads, then the additional sector-erase command was accepted. |
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